A die selection and matching method with two stages for yield enhancement of 3-D memories

Wooheon Kang, Changwook Lee, Keewon Cho, Sungho Kang

Research output: Contribution to journalConference article

3 Citations (Scopus)


Three-dimensional (3-D) memories using through-silicon-vias (TSVs) as vertical buses across memory layers has regarded as one of 3-D integrated circuits (ICs) technology. The memory dies to stack together in a 3-D memory are selected by a die selection method. In order to improve yield of 3-D memories, redundancy sharing between inter-die using TSVs is an effective strategy. With the redundancy sharing strategy, the bad memory dies can become good 3-D memories through matching the good memory dies. To support die selection and matching efficiently, a novel redundancy analysis (RA) algorithm, which considers various repair solutions, is proposed. Because the repair solutions can be various, the proposed die selection and matching is performed with two stages; general die selection and matching method in the first stage and re-matched remained memory dies, after the first stage, applying other repair solutions in the second stage. Thus, the proposed die selection and matching algorithm using the proposed RA algorithm can improve yield of 3-D memories. The experimental results show that the proposed die selection and matching method can achieve higher yield of 3-D memories than that of the previous state-of-the-art the die selection and matching methods.

Original languageEnglish
Article number6690658
Pages (from-to)301-306
Number of pages6
JournalProceedings of the Asian Test Symposium
Publication statusPublished - 2013 Jan 1
Event2013 22nd Asian Test Symposium, ATS 2013 - Yilan, Taiwan, Province of China
Duration: 2013 Nov 182013 Nov 21


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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