A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator

Kyungho Ryu, Dong Hoon Jung, Seongook Jung

Research output: Contribution to journalArticle

20 Citations (Scopus)

Abstract

A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm 2 and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.

Original languageEnglish
Article number6129518
Pages (from-to)1860-1870
Number of pages11
JournalIEEE Transactions on Circuits and Systems I: Regular Papers
Volume59
Issue number9
DOIs
Publication statusPublished - 2012 Jan 19

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Jitter
Clocks
Detectors
Electric power utilization
Bandwidth
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

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abstract = "A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm 2 and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.",
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A DLL with dual edge triggered phase detector for fast lock and low jitter clock generator. / Ryu, Kyungho; Jung, Dong Hoon; Jung, Seongook.

In: IEEE Transactions on Circuits and Systems I: Regular Papers, Vol. 59, No. 9, 6129518, 19.01.2012, p. 1860-1870.

Research output: Contribution to journalArticle

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