A DLL based on a dual edge triggered phase detector (DET-PD) is proposed for a clock generator in low-power systems. The proposed DLL has a faster lock speed with the same loop dynamics compared to the conventional DLL based on a single-edge triggered phase detector (SET-PD). The proposed DET-PD solves the problem of a narrow capture range or low phase detector gain associated with the conventional DET-PD. In addition, the proposed duty cycle difference compensation circuit (DDC) prevents the increase in the phase offset when the two inputs to the DET-PD have different duty cycle. It also controls the DLL bandwidth to maintain the DLL jitter by controlling the negative edge delay difference tracking. Finally, the proposed duty cycle keeper (DCK) enlarges the duty cycle keeping range of the DLL output. The proposed DLL is fabricated using 0.18-μm process technology. It has an area of 0.035 mm 2 and a power consumption of 19 mW at 800 MHz operation. Its lock speed is over 1.9 times faster than that of the DLL based on the SET-PD without degrading the jitter.
|Number of pages||11|
|Journal||IEEE Transactions on Circuits and Systems I: Regular Papers|
|Publication status||Published - 2012|
Bibliographical noteFunding Information:
Manuscript received December 29, 2010; revised June 20, 2011, September 10, 2011; accepted November 01, 2011. Date of publication January 12, 2012; date of current version August 24, 2012. This work was supported in part by the IT R&D program of MKE/KEIT, 10034834, a development of ASIC chip for next generation high speed ATE. This paper was recommended by Associate Editor A. Sheikholeslami.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering