Translation look-aside buffers (TLBs) are small caches to speed-up address translation in processors with virtual memory. There are many methods for improving TLB performance, such as increasing the number of entries in TLB and supporting large page or multiple page sizes. The best way is to support multiple page sizes, but any operating system doesn't support multiple page sizes in user mode. Also software must select a proper page-size assignment policy to take advantage of the larger pages. So, we propose a new structure of TLB supporting two pages to obtain the effect of multiple page sizes with high performance and at low cost without operating system support. According to result of comparison and analysis, the proposed method with fewer entries results in similar performance compared with the conventional TLB with many entries. Also in the case of same area size, it is shown that miss ratio of the proposed TLB can be reduced by as much as 90% comparing with conventional fully-associative TLB.