A Fast Full-System Simulation Environment for Memory System Evaluation

Taeyang Jeong; Sangwoo Han; Eui Young Chung

doi:10.1109/ISOCC50952.2020.9333006

A Fast Full-System Simulation Environment for Memory System Evaluation

Taeyang Jeong, Sangwoo Han, Eui Young Chung

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, we propose a fast full-system simulation environment that complements the shortcomings of each simulator to evaluate the memory system. We used a full-system simulator as a memory trace generator, except for the unnecessary details of it. Generated traces become inputs of trace-driven memory simulator. We also fine-Tuned the memory simulator to get higher accuracy. The results show that the simulation can run at a speed of 1/7158x of the real system on average and the accuracy of memory system simulation is achieved by averaging 92.5% for bandwidth and 85.7% for latency.

Original language	English
Title of host publication	Proceedings - International SoC Design Conference, ISOCC 2020
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	99-100
Number of pages	2
ISBN (Electronic)	9781728183312
DOIs	https://doi.org/10.1109/ISOCC50952.2020.9333006
Publication status	Published - 2020 Oct 21
Event	17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of Duration: 2020 Oct 21 → 2020 Oct 24

Publication series

Name	Proceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference	17th International System-on-Chip Design Conference, ISOCC 2020
Country	Korea, Republic of
City	Yeosu
Period	20/10/21 → 20/10/24

Bibliographical note

Funding Information:
IV. CONCLUSTION In this paper, we propose a fast and accurate full-system simulation environment. We combine the cycle-accurate full-system simulator with the trace-driven memory simulator and modify each of them to compensate disadvantages. The results show that on average, the slow-down of simulation speed is 1/7168x of the speed of the real system and the accuracies of bandwidth and latency are 92.5% and 85.7%.G ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy) (10080722) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. And the chip fabrication and EDA Tool were supported by the IC Design Education Center.

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

Energy Engineering and Power Technology
Electrical and Electronic Engineering
Instrumentation
Artificial Intelligence
Hardware and Architecture

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10.1109/ISOCC50952.2020.9333006

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Jeong, T., Han, S., & Chung, E. Y. (2020). A Fast Full-System Simulation Environment for Memory System Evaluation. In Proceedings - International SoC Design Conference, ISOCC 2020 (pp. 99-100). [9333006] (Proceedings - International SoC Design Conference, ISOCC 2020). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISOCC50952.2020.9333006

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author = "Taeyang Jeong and Sangwoo Han and Chung, {Eui Young}",

note = "Funding Information: IV. CONCLUSTION In this paper, we propose a fast and accurate full-system simulation environment. We combine the cycle-accurate full-system simulator with the trace-driven memory simulator and modify each of them to compensate disadvantages. The results show that on average, the slow-down of simulation speed is 1/7168x of the speed of the real system and the accuracies of bandwidth and latency are 92.5% and 85.7%.G ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy) (10080722) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. And the chip fabrication and EDA Tool were supported by the IC Design Education Center. Publisher Copyright: {\textcopyright} 2020 IEEE.; 17th International System-on-Chip Design Conference, ISOCC 2020 ; Conference date: 21-10-2020 Through 24-10-2020",

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Jeong, T, Han, S & Chung, EY 2020, A Fast Full-System Simulation Environment for Memory System Evaluation. in Proceedings - International SoC Design Conference, ISOCC 2020., 9333006, Proceedings - International SoC Design Conference, ISOCC 2020, Institute of Electrical and Electronics Engineers Inc., pp. 99-100, 17th International System-on-Chip Design Conference, ISOCC 2020, Yeosu, Korea, Republic of, 20/10/21. https://doi.org/10.1109/ISOCC50952.2020.9333006

A Fast Full-System Simulation Environment for Memory System Evaluation. / Jeong, Taeyang; Han, Sangwoo; Chung, Eui Young.

Proceedings - International SoC Design Conference, ISOCC 2020. Institute of Electrical and Electronics Engineers Inc., 2020. p. 99-100 9333006 (Proceedings - International SoC Design Conference, ISOCC 2020).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: IV. CONCLUSTION In this paper, we propose a fast and accurate full-system simulation environment. We combine the cycle-accurate full-system simulator with the trace-driven memory simulator and modify each of them to compensate disadvantages. The results show that on average, the slow-down of simulation speed is 1/7168x of the speed of the real system and the accuracies of bandwidth and latency are 92.5% and 85.7%.G ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy) (10080722) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. And the chip fabrication and EDA Tool were supported by the IC Design Education Center. Publisher Copyright: © 2020 IEEE.

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Y1 - 2020/10/21

N2 - In this paper, we propose a fast full-system simulation environment that complements the shortcomings of each simulator to evaluate the memory system. We used a full-system simulator as a memory trace generator, except for the unnecessary details of it. Generated traces become inputs of trace-driven memory simulator. We also fine-Tuned the memory simulator to get higher accuracy. The results show that the simulation can run at a speed of 1/7158x of the real system on average and the accuracy of memory system simulation is achieved by averaging 92.5% for bandwidth and 85.7% for latency.

AB - In this paper, we propose a fast full-system simulation environment that complements the shortcomings of each simulator to evaluate the memory system. We used a full-system simulator as a memory trace generator, except for the unnecessary details of it. Generated traces become inputs of trace-driven memory simulator. We also fine-Tuned the memory simulator to get higher accuracy. The results show that the simulation can run at a speed of 1/7158x of the real system on average and the accuracy of memory system simulation is achieved by averaging 92.5% for bandwidth and 85.7% for latency.

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A Fast Full-System Simulation Environment for Memory System Evaluation

Abstract

Publication series

Conference

Bibliographical note

All Science Journal Classification (ASJC) codes

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