A Fast Full-System Simulation Environment for Memory System Evaluation

Taeyang Jeong, Sangwoo Han, Eui Young Chung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, we propose a fast full-system simulation environment that complements the shortcomings of each simulator to evaluate the memory system. We used a full-system simulator as a memory trace generator, except for the unnecessary details of it. Generated traces become inputs of trace-driven memory simulator. We also fine-Tuned the memory simulator to get higher accuracy. The results show that the simulation can run at a speed of 1/7158x of the real system on average and the accuracy of memory system simulation is achieved by averaging 92.5% for bandwidth and 85.7% for latency.

Original languageEnglish
Title of host publicationProceedings - International SoC Design Conference, ISOCC 2020
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages99-100
Number of pages2
ISBN (Electronic)9781728183312
DOIs
Publication statusPublished - 2020 Oct 21
Event17th International System-on-Chip Design Conference, ISOCC 2020 - Yeosu, Korea, Republic of
Duration: 2020 Oct 212020 Oct 24

Publication series

NameProceedings - International SoC Design Conference, ISOCC 2020

Conference

Conference17th International System-on-Chip Design Conference, ISOCC 2020
Country/TerritoryKorea, Republic of
CityYeosu
Period20/10/2120/10/24

Bibliographical note

Funding Information:
IV. CONCLUSTION In this paper, we propose a fast and accurate full-system simulation environment. We combine the cycle-accurate full-system simulator with the trace-driven memory simulator and modify each of them to compensate disadvantages. The results show that on average, the slow-down of simulation speed is 1/7168x of the speed of the real system and the accuracies of bandwidth and latency are 92.5% and 85.7%.G ACKNOWLEDGMENT This research was supported by the MOTIE(Ministry of Trade, Industry & Energy) (10080722) and KSRC(Korea Semiconductor Research Consortium) support program for the development of the future semiconductor device. And the chip fabrication and EDA Tool were supported by the IC Design Education Center.

Publisher Copyright:
© 2020 IEEE.

All Science Journal Classification (ASJC) codes

  • Energy Engineering and Power Technology
  • Electrical and Electronic Engineering
  • Instrumentation
  • Artificial Intelligence
  • Hardware and Architecture

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