A flash-aware write buffer scheme to enhance the performance of superblock-based NAND flash storage systems

Ning Lu, In Sung Choi, Shin-Dug Kim

Research output: Contribution to journalArticle

Abstract

Most superblock-based NAND flash storage systems employ a high-speed write buffer to enhance their writing performance. The main objective is to bind data of adjacent addresses as much as possible in order to transform random data into sequential data, which then facilitates interleaving in the storage system. We have designed a new superblock-based buffer scheme for NAND flash storage systems that improves on traditional schemes. For buffer management, a series of lists need to be specified to monitor the dataflow changes in the current state of the buffered data and the NAND flash memory in order to maximize interleaving during the flush operation. Experimental results show that the proposed scheme achieves higher write speed performance in almost all configurations, with greater than 50% speedup in some cases. Our proposed flash-aware write buffer (FAWB) scheme achieves this higher write performance with a required buffer space of only 1/4th-1/8th that of other schemes, resulting in higher efficiency.

Original languageEnglish
Pages (from-to)345-357
Number of pages13
JournalMicroprocessors and Microsystems
Volume37
Issue number3
DOIs
Publication statusPublished - 2013 Jan 1

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Flash memory

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

Cite this

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A flash-aware write buffer scheme to enhance the performance of superblock-based NAND flash storage systems. / Lu, Ning; Choi, In Sung; Kim, Shin-Dug.

In: Microprocessors and Microsystems, Vol. 37, No. 3, 01.01.2013, p. 345-357.

Research output: Contribution to journalArticle

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