Abstract
An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proff-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 × 10 6 synapses/s · mm 2 and the energy consumption is 10 -9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.
| Original language | English |
|---|---|
| Pages (from-to) | 1055-1063 |
| Number of pages | 9 |
| Journal | IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications |
| Volume | 46 |
| Issue number | 9 |
| DOIs | |
| Publication status | Published - 1999 Sep |
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
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Han, G., & Sánchez-Sinencio, E. (1999). a flexible and expendable neuroimage processor architecture. IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, 46(9), 1055-1063. https://doi.org/10.1109/81.788807