a flexible and expendable neuroimage processor architecture

Gunhee Han; Edgar Sánchez-Sinencio

doi:10.1109/81.788807

a flexible and expendable neuroimage processor architecture

Gunhee Han, Edgar Sánchez-Sinencio

School of Integrated Technology

Research output: Contribution to journal › Article › peer-review

5 Citations (Scopus)

Abstract

An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proff-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 × 10 ⁶ synapses/s · mm ² and the energy consumption is 10 ^-9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.

Original language	English
Pages (from-to)	1055-1063
Number of pages	9
Journal	IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications
Volume	46
Issue number	9
DOIs	https://doi.org/10.1109/81.788807
Publication status	Published - 1999 Sep

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

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@article{dc5d5bdab1684fcc9ae4421e88f92ef2,

title = "a flexible and expendable neuroimage processor architecture",

abstract = "An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proff-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 × 10 6 synapses/s · mm 2 and the energy consumption is 10 -9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.",

author = "Gunhee Han and Edgar S{\'a}nchez-Sinencio",

year = "1999",

month = sep,

doi = "10.1109/81.788807",

language = "English",

volume = "46",

pages = "1055--1063",

journal = "IEEE Transactions on Circuits and Systems II: Express Briefs",

issn = "1549-8328",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "9",

}

TY - JOUR

T1 - a flexible and expendable neuroimage processor architecture

AU - Han, Gunhee

AU - Sánchez-Sinencio, Edgar

PY - 1999/9

Y1 - 1999/9

N2 - An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proff-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 × 10 6 synapses/s · mm 2 and the energy consumption is 10 -9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.

AB - An analog versatile neuroimage processor (VNIP) architecture is proposed here. VNIP can process various types of neural network and image processing structures, without any hardware modification. The structure allows unlimited expansion of network size and the compensation of process variation. The proff-of-concept chip is implemented, using a combination of continuous-time multiplier and switched-capacitor techniques. The throughput is 12 × 10 6 synapses/s · mm 2 and the energy consumption is 10 -9 J/synapse. A test chip was fabricated, using a 1.2-μm double-poly CMOS process and tested, verifying the flexibility and expandability of the architecture.

UR - http://www.scopus.com/inward/record.url?scp=0033320110&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0033320110&partnerID=8YFLogxK

U2 - 10.1109/81.788807

DO - 10.1109/81.788807

M3 - Article

AN - SCOPUS:0033320110

VL - 46

SP - 1055

EP - 1063

JO - IEEE Transactions on Circuits and Systems II: Express Briefs

JF - IEEE Transactions on Circuits and Systems II: Express Briefs

SN - 1549-8328

IS - 9

ER -

a flexible and expendable neuroimage processor architecture

Abstract

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