A floating point divider performing IEEE rounding and quotient conversion in parallel

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.

Original languageEnglish
Pages (from-to)568-581
Number of pages14
JournalLecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics)
Volume3189
Publication statusPublished - 2004 Dec 1

Fingerprint

Rounding
Adders
Floating point
Quotient
Hardware
Execution Time
Normalization
Processing
Division
High Speed
Design Efficiency
Recurrence
Increment
Multiplier
Cycle
Unit

All Science Journal Classification (ASJC) codes

  • Theoretical Computer Science
  • Computer Science(all)

Cite this

@article{69da4bffca5d4886b782fde29d96eed9,
title = "A floating point divider performing IEEE rounding and quotient conversion in parallel",
abstract = "Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.",
author = "Park, {Woo Chan} and Han, {Tack Don} and Yang, {Sung Bong}",
year = "2004",
month = "12",
day = "1",
language = "English",
volume = "3189",
pages = "568--581",
journal = "Lecture Notes in Computer Science",
issn = "0302-9743",
publisher = "Springer Verlag",

}

TY - JOUR

T1 - A floating point divider performing IEEE rounding and quotient conversion in parallel

AU - Park, Woo Chan

AU - Han, Tack Don

AU - Yang, Sung Bong

PY - 2004/12/1

Y1 - 2004/12/1

N2 - Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.

AB - Processing floating point division generally consists of SRT recurrence, quotient conversion, rounding, and normalization steps. In the rounding step, a high speed adder is required for increment operation, increasing the overall execution time. In this paper, a floating point divider performing quotient conversion and rounding in parallel is presented by analyzing the operational characteristics of floating point division. The proposed floating point divider does not require any additional execution time, nor does it need any high speed adder for the rounding step. The proposed divider can execute quotient conversion, rounding, and normalization within one cycle. To support design efficiency, the quotient conversion/rounding unit of the proposed divider can be shared efficiently with the addition/rounding hardware for floating point multiplier.

UR - http://www.scopus.com/inward/record.url?scp=35048887034&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=35048887034&partnerID=8YFLogxK

M3 - Article

VL - 3189

SP - 568

EP - 581

JO - Lecture Notes in Computer Science

JF - Lecture Notes in Computer Science

SN - 0302-9743

ER -