A Framework for Architecture-Level Power, Area, Thermal Simulation and Its Application to Network-on-Chip Design Exploration

Computer Science

• Delay() 100%
• Networks on Chips 100%
• Energy Delay Product 100%
• Modeling Framework 50%
• Performance Computer 50%
• Energy Dissipation 50%
• Memory Controller 50%
• Architecture Level 50%
• Design Exploration 50%
• Manycore System 50%
• Exascale System 50%
• Participatory Design 50%
• Total Power Dissipation 50%

Engineering

• Network-on-Chip 100%
• Computer Simulation 50%
• Compute 50%
• Energy Dissipation 50%
• Core Network 50%
• Functionality 50%
• Temperature Change 50%
• Thermal Simulation 50%
• Memory Controller 50%
• Chip Memory 50%