A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization

Ki Bum Chun, Changmin Lee, Won Woo Ro

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.

Original languageEnglish
Title of host publication2015 International Symposium on Consumer Electronics, ISCE 2015
PublisherInstitute of Electrical and Electronics Engineers Inc.
ISBN (Electronic)9781467373654
DOIs
Publication statusPublished - 2015 Aug 4
EventIEEE International Symposium on Consumer Electronics, ISCE 2015 - Madrid, Spain
Duration: 2015 Jun 242015 Jun 26

Publication series

NameProceedings of the International Symposium on Consumer Electronics, ISCE
Volume2015-August

Other

OtherIEEE International Symposium on Consumer Electronics, ISCE 2015
CountrySpain
CityMadrid
Period15/6/2415/6/26

Fingerprint

Delay circuits
Networks (circuits)
Electric potential
Costs

All Science Journal Classification (ASJC) codes

  • Engineering(all)

Cite this

Chun, K. B., Lee, C., & Ro, W. W. (2015). A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. In 2015 International Symposium on Consumer Electronics, ISCE 2015 [7177841] (Proceedings of the International Symposium on Consumer Electronics, ISCE; Vol. 2015-August). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ISCE.2015.7177841
Chun, Ki Bum ; Lee, Changmin ; Ro, Won Woo. / A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. 2015 International Symposium on Consumer Electronics, ISCE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. (Proceedings of the International Symposium on Consumer Electronics, ISCE).
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abstract = "DVFS techniques that have more than one operating mode provide several pairs of operating frequencies and supply voltages. As circuit delays vary with supply voltages, an effort to optimize the circuit delays is necessarily required. The primary impediment to optimize the extra circuits is an increase of power overheads because it prevents satisfying power constraints of the DVFS design. In this paper, we propose an analytic model to find energy efficient points regarding the power overheads induced by the extra circuit costs. The analytic model consists of two parameters: frequency scaling factor and operational duty cycle. In a parameter sweep, optimal frequencies of a low-power mode can be estimated as compared with a high-performance mode.",
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Chun, KB, Lee, C & Ro, WW 2015, A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. in 2015 International Symposium on Consumer Electronics, ISCE 2015., 7177841, Proceedings of the International Symposium on Consumer Electronics, ISCE, vol. 2015-August, Institute of Electrical and Electronics Engineers Inc., IEEE International Symposium on Consumer Electronics, ISCE 2015, Madrid, Spain, 15/6/24. https://doi.org/10.1109/ISCE.2015.7177841

A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. / Chun, Ki Bum; Lee, Changmin; Ro, Won Woo.

2015 International Symposium on Consumer Electronics, ISCE 2015. Institute of Electrical and Electronics Engineers Inc., 2015. 7177841 (Proceedings of the International Symposium on Consumer Electronics, ISCE; Vol. 2015-August).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chun KB, Lee C, Ro WW. A frequency scaling model for energy efficient DVFS designs based on circuit delay optimization. In 2015 International Symposium on Consumer Electronics, ISCE 2015. Institute of Electrical and Electronics Engineers Inc. 2015. 7177841. (Proceedings of the International Symposium on Consumer Electronics, ISCE). https://doi.org/10.1109/ISCE.2015.7177841