A giga-b/s CMOS clock and data recovery circuit with a adaptive phase detector were studied. It was found that high frequency jitter is one of the major performance-limiting factor. It was also found that the phase detector is able to suppress the noise and stable clock generation.
|Number of pages||4|
|Journal||IEICE Transactions on Communications|
|Publication status||Published - 2003 Jul|
All Science Journal Classification (ASJC) codes
- Computer Networks and Communications
- Electrical and Electronic Engineering