A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector

Jae Wook Lee, Cheon O. Lee, Woo Young Choi

Research output: Contribution to journalArticle

Abstract

A giga-b/s CMOS clock and data recovery circuit with a adaptive phase detector were studied. It was found that high frequency jitter is one of the major performance-limiting factor. It was also found that the phase detector is able to suppress the noise and stable clock generation.

Original languageEnglish
Pages (from-to)2186-2189
Number of pages4
JournalIEICE Transactions on Communications
VolumeE86-B
Issue number7
Publication statusPublished - 2003 Jan 1

Fingerprint

Clock and data recovery circuits (CDR circuits)
Detectors
Jitter
Clocks

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

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A Giga-b/s CMOS Clock and Data Recovery Circuit with a Novel Adaptive Phase Detector. / Lee, Jae Wook; Lee, Cheon O.; Choi, Woo Young.

In: IEICE Transactions on Communications, Vol. E86-B, No. 7, 01.01.2003, p. 2186-2189.

Research output: Contribution to journalArticle

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