A hardware architecture for intra-prediction of H.264/AVC

Intra-prediction of H.264/AVC provides great contribution to I-picture coding efficiency by predicting pixel values from adjacent pixels. But it is one of major complexity-raising sources caused from checking 17 candidate modes for every macroblock. This paper presents a dedicated hardware structure for intra-prediction that is designed by modifying a conventional 1-D systolic array for motion estimation. Only attaching multiplexers to it, we can obtain a systolic array that can perform both intra-prediction and inter-prediction. For parallel execution, we modify the original intra-prediction algorithm slightly, but it does not nearly affect PSNR and the total size. Our architecture yields 10 to 40 times higher performance than that achieved by ARM-based systems, being compared by instruction counts for arithmetic operations.