A Hardware Architecture for the Affine-Invariant Extension of SIFT

Joohyuk Yum, Chul Hee Lee, Jinwoo Park, Jin Sung Kim, Hyuk Jae Lee

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640×480) video at 20 fps.

Original languageEnglish
Article number8010882
Pages (from-to)3251-3261
Number of pages11
JournalIEEE Transactions on Circuits and Systems for Video Technology
Volume28
Issue number11
DOIs
Publication statusPublished - 2018 Nov

All Science Journal Classification (ASJC) codes

  • Media Technology
  • Electrical and Electronic Engineering

Fingerprint Dive into the research topics of 'A Hardware Architecture for the Affine-Invariant Extension of SIFT'. Together they form a unique fingerprint.

  • Cite this