Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640×480) video at 20 fps.
|Number of pages||11|
|Journal||IEEE Transactions on Circuits and Systems for Video Technology|
|Publication status||Published - 2018 Nov|
Bibliographical noteFunding Information:
Manuscript received November 14, 2016; revised July 11, 2017; accepted July 29, 2017. Date of publication August 15, 2017; date of current version November 5, 2018. This work was supported in part by Samsung electronics and in part by the Korea Institute for Advancement of Technology grant funded by the Korean government (Ministry of Trade, Industry and Energy, HRD Program for Software-SoC convergence) under Grant N0001883. This paper was recommended by Associate Editor P. K. Meher. (Corresponding author: Jin-Sung Kim.) J. Yum is with the System LSI Division, Samsung Electronics Corporation, Hwaseong 18448, South Korea.
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All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering