A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

Deruo Cheng; Yiqiong Shi; Bah Hwee Gwee; Kar Ann Toh; Tong Lin

doi:10.1109/MIS.2018.2886669

A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

Deruo Cheng, Yiqiong Shi, Bah Hwee Gwee, Kar Ann Toh, Tong Lin

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

6 Citations (Scopus)

Abstract

A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-The-Art deep submicron IC chips.

Original language	English
Article number	8574979
Pages (from-to)	36-43
Number of pages	8
Journal	IEEE Intelligent Systems
Volume	34
Issue number	2
DOIs	https://doi.org/10.1109/MIS.2018.2886669
Publication status	Published - 2019 Mar 1

Bibliographical note

Publisher Copyright:
© 2001-2011 IEEE.

All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Artificial Intelligence

Access to Document

10.1109/MIS.2018.2886669

Cite this

@article{37f920b5bb3f459abd4bbc44662c326a,

title = "A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images",

abstract = "A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-The-Art deep submicron IC chips.",

author = "Deruo Cheng and Yiqiong Shi and Gwee, {Bah Hwee} and Toh, {Kar Ann} and Tong Lin",

note = "Publisher Copyright: {\textcopyright} 2001-2011 IEEE.",

year = "2019",

month = mar,

day = "1",

doi = "10.1109/MIS.2018.2886669",

language = "English",

volume = "34",

pages = "36--43",

journal = "IEEE Intelligent Systems and Their Applications",

issn = "1541-1672",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

number = "2",

}

TY - JOUR

T1 - A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

AU - Cheng, Deruo

AU - Shi, Yiqiong

AU - Gwee, Bah Hwee

AU - Toh, Kar Ann

AU - Lin, Tong

PY - 2019/3/1

Y1 - 2019/3/1

N2 - A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-The-Art deep submicron IC chips.

AB - A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-The-Art deep submicron IC chips.

UR - http://www.scopus.com/inward/record.url?scp=85058663657&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=85058663657&partnerID=8YFLogxK

U2 - 10.1109/MIS.2018.2886669

DO - 10.1109/MIS.2018.2886669

M3 - Article

AN - SCOPUS:85058663657

VL - 34

SP - 36

EP - 43

JO - IEEE Intelligent Systems and Their Applications

JF - IEEE Intelligent Systems and Their Applications

SN - 1541-1672

IS - 2

M1 - 8574979

ER -

A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

Abstract

Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this