A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

Deruo Cheng; Yiqiong Shi; Bah Hwee Gwee; Kar Ann Toh; Tong Lin

doi:10.1109/MIS.2018.2886669

A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

Deruo Cheng, Yiqiong Shi, Bah Hwee Gwee, Kar Ann Toh, Tong Lin

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article

Abstract

A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-The-Art deep submicron IC chips.

Original language	English
Article number	8574979
Pages (from-to)	36-43
Number of pages	8
Journal	IEEE Intelligent Systems
Volume	34
Issue number	2
DOIs	https://doi.org/10.1109/MIS.2018.2886669
Publication status	Published - 2019 Mar 1

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All Science Journal Classification (ASJC) codes

Computer Networks and Communications
Artificial Intelligence

Cite this

Cheng, D., Shi, Y., Gwee, B. H., Toh, K. A., & Lin, T. (2019). A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. IEEE Intelligent Systems, 34(2), 36-43. [8574979]. https://doi.org/10.1109/MIS.2018.2886669

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Access to Document

10.1109/MIS.2018.2886669