A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images

Deruo Cheng, Yiqiong Shi, Bah Hwee Gwee, Kar Ann Toh, Tong Lin

Research output: Contribution to journalArticle

Abstract

A robust and accurate machine learning based hierarchical multiclassifier system is proposed to automate the retrieval of interconnection information from delayered integrated circuits images. The proposed system replaces labor-intensive manual annotation process and provides an effective approach for the automated analysis of state-of-The-Art deep submicron IC chips.

Original languageEnglish
Article number8574979
Pages (from-to)36-43
Number of pages8
JournalIEEE Intelligent Systems
Volume34
Issue number2
DOIs
Publication statusPublished - 2019 Mar 1

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Hierarchical systems
Integrated circuits
Learning systems
Personnel

All Science Journal Classification (ASJC) codes

  • Computer Networks and Communications
  • Artificial Intelligence

Cite this

Cheng, Deruo ; Shi, Yiqiong ; Gwee, Bah Hwee ; Toh, Kar Ann ; Lin, Tong. / A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. In: IEEE Intelligent Systems. 2019 ; Vol. 34, No. 2. pp. 36-43.
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A Hierarchical Multiclassifier System for Automated Analysis of Delayered IC Images. / Cheng, Deruo; Shi, Yiqiong; Gwee, Bah Hwee; Toh, Kar Ann; Lin, Tong.

In: IEEE Intelligent Systems, Vol. 34, No. 2, 8574979, 01.03.2019, p. 36-43.

Research output: Contribution to journalArticle

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