A high dynamic range CMOS image sensor with in-pixel floating-node analog memory for pixel level integration time control

Sang Wook Han, Seong Jin Kim, Jae Hyuk Choi, Choong Ki Kim, Euisik Yoon

Research output: Chapter in Book/Report/Conference proceedingConference contribution

13 Citations (Scopus)

Abstract

In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. We can implement true CDS technique to reduce reset noise without any additional hardware because we use a floating-node parasitic capacitor as an analog memory. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB. To the best of our knowledge, this is the first report on the use of pixel-node parasitic capacitor as an analog memory for the extension of dynamic range.

Original languageEnglish
Title of host publication2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
Pages25-26
Number of pages2
Publication statusPublished - 2006
Event2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States
Duration: 2006 Jun 152006 Jun 17

Publication series

NameIEEE Symposium on VLSI Circuits, Digest of Technical Papers

Conference

Conference2006 Symposium on VLSI Circuits, VLSIC
Country/TerritoryUnited States
CityHonolulu, HI
Period06/6/1506/6/17

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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