Abstract
In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. We can implement true CDS technique to reduce reset noise without any additional hardware because we use a floating-node parasitic capacitor as an analog memory. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB. To the best of our knowledge, this is the first report on the use of pixel-node parasitic capacitor as an analog memory for the extension of dynamic range.
| Original language | English |
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| Title of host publication | 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers |
| Pages | 25-26 |
| Number of pages | 2 |
| Publication status | Published - 2006 |
| Event | 2006 Symposium on VLSI Circuits, VLSIC - Honolulu, HI, United States Duration: 2006 Jun 15 → 2006 Jun 17 |
Publication series
| Name | IEEE Symposium on VLSI Circuits, Digest of Technical Papers |
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Conference
| Conference | 2006 Symposium on VLSI Circuits, VLSIC |
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| Country | United States |
| City | Honolulu, HI |
| Period | 06/6/15 → 06/6/17 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Electrical and Electronic Engineering
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Cite this
Han, S. W., Kim, S. J., Choi, J. H., Kim, C. K., & Yoon, E. (2006). A high dynamic range CMOS image sensor with in-pixel floating-node analog memory for pixel level integration time control. In 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers (pp. 25-26). [1705294] (IEEE Symposium on VLSI Circuits, Digest of Technical Papers).