TY - GEN
T1 - A high dynamic range CMOS image sensor with in-pixel floating-node analog memory for pixel level integration time control
AU - Han, Sang Wook
AU - Kim, Seong Jin
AU - Choi, Jae Hyuk
AU - Kim, Choong Ki
AU - Yoon, Euisik
N1 - Copyright:
Copyright 2008 Elsevier B.V., All rights reserved.
PY - 2006
Y1 - 2006
N2 - In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. We can implement true CDS technique to reduce reset noise without any additional hardware because we use a floating-node parasitic capacitor as an analog memory. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB. To the best of our knowledge, this is the first report on the use of pixel-node parasitic capacitor as an analog memory for the extension of dynamic range.
AB - In this paper we report a high dynamic range CMOS image sensor (CIS) with in-pixel floating-node analog memory for pixel level integration time control. Each pixel has different integration time based upon the amount of its previous frame illumination. We can implement true CDS technique to reduce reset noise without any additional hardware because we use a floating-node parasitic capacitor as an analog memory. In the fabricated test sensor, we could achieve the extended dynamic range by more than 42dB. To the best of our knowledge, this is the first report on the use of pixel-node parasitic capacitor as an analog memory for the extension of dynamic range.
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M3 - Conference contribution
AN - SCOPUS:34548850418
SN - 1424400066
SN - 9781424400065
T3 - IEEE Symposium on VLSI Circuits, Digest of Technical Papers
SP - 25
EP - 26
BT - 2006 Symposium on VLSI Circuits, VLSIC - Digest of Technical Papers
T2 - 2006 Symposium on VLSI Circuits, VLSIC
Y2 - 15 June 2006 through 17 June 2006
ER -