A high-level signal integrity fault model and test methodology for long on-chip interconnections

Sunghoon Chun, Yongjoon Kim, Taejin Kim, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, considering the interconnection topology information, an abstract model and a new test pattern generation method of signal integrity problems on interconnects are proposed. In addition, previous SPICE-based pattern generation methods are too complex and time consuming to generate test patterns for signal integrity faults. To more accurately detect signal integrity defects on practical on-chip interconnection lines and avoid time consuming for interconnection analysis, in this paper, we propose a new high-level signal integrity fault model to estimate noise effects based on process variation and interconnect signal transition. Experimental results show that the proposed signal integrity fault model is more exact for long interconnects than previous approaches. In addition, the proposed method is much faster than the SPICE-based pattern generation method.

Original languageEnglish
Title of host publicationProceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009
Pages152-157
Number of pages6
DOIs
Publication statusPublished - 2009 Nov 2
Event2009 27th IEEE VLSI Test Symposium, VTS 2009 - Santa Cruz, CA, United States
Duration: 2009 May 32009 May 7

Other

Other2009 27th IEEE VLSI Test Symposium, VTS 2009
CountryUnited States
CitySanta Cruz, CA
Period09/5/309/5/7

Fingerprint

SPICE
Topology
Defects

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering

Cite this

Chun, S., Kim, Y., Kim, T., & Kang, S. (2009). A high-level signal integrity fault model and test methodology for long on-chip interconnections. In Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009 (pp. 152-157). [5116626] https://doi.org/10.1109/VTS.2009.38
Chun, Sunghoon ; Kim, Yongjoon ; Kim, Taejin ; Kang, Sungho. / A high-level signal integrity fault model and test methodology for long on-chip interconnections. Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009. 2009. pp. 152-157
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Chun, S, Kim, Y, Kim, T & Kang, S 2009, A high-level signal integrity fault model and test methodology for long on-chip interconnections. in Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009., 5116626, pp. 152-157, 2009 27th IEEE VLSI Test Symposium, VTS 2009, Santa Cruz, CA, United States, 09/5/3. https://doi.org/10.1109/VTS.2009.38

A high-level signal integrity fault model and test methodology for long on-chip interconnections. / Chun, Sunghoon; Kim, Yongjoon; Kim, Taejin; Kang, Sungho.

Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009. 2009. p. 152-157 5116626.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Chun S, Kim Y, Kim T, Kang S. A high-level signal integrity fault model and test methodology for long on-chip interconnections. In Proceedings - 2009 27th IEEE VLSI Test Symposium, VTS 2009. 2009. p. 152-157. 5116626 https://doi.org/10.1109/VTS.2009.38