A high performance motion vector processor IP design for H.264/AVC

Kiwon Yoo, Seungho Park, Hyunsuk Ko, Kwanghoon Sohn

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 × 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 × 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.

Original languageEnglish
Title of host publication12th IEEE International Symposium on Consumer Electronics - ISCE2008
DOIs
Publication statusPublished - 2008 Sep 17
Event12th IEEE International Symposium on Consumer Electronics - ISCE2008 - Vilamoura, Portugal
Duration: 2008 Apr 142008 Apr 16

Publication series

NameProceedings of the International Symposium on Consumer Electronics, ISCE

Other

Other12th IEEE International Symposium on Consumer Electronics - ISCE2008
CountryPortugal
CityVilamoura
Period08/4/1408/4/16

All Science Journal Classification (ASJC) codes

  • Engineering(all)

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  • Cite this

    Yoo, K., Park, S., Ko, H., & Sohn, K. (2008). A high performance motion vector processor IP design for H.264/AVC. In 12th IEEE International Symposium on Consumer Electronics - ISCE2008 [4559504] (Proceedings of the International Symposium on Consumer Electronics, ISCE). https://doi.org/10.1109/ISCE.2008.4559504