A high performance motion vector processor IP design for H.264/AVC

Kiwon Yoo; Seungho Park; Hyunsuk Ko; Kwanghoon Sohn

doi:10.1109/ISCE.2008.4559504

A high performance motion vector processor IP design for H.264/AVC

Kiwon Yoo, Seungho Park, Hyunsuk Ko, Kwanghoon Sohn

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

Abstract

In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 × 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 × 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.

Original language	English
Title of host publication	12th IEEE International Symposium on Consumer Electronics - ISCE2008
DOIs	https://doi.org/10.1109/ISCE.2008.4559504
Publication status	Published - 2008
Event	12th IEEE International Symposium on Consumer Electronics - ISCE2008 - Vilamoura, Portugal Duration: 2008 Apr 14 → 2008 Apr 16

Publication series

Name	Proceedings of the International Symposium on Consumer Electronics, ISCE

Other

Other	12th IEEE International Symposium on Consumer Electronics - ISCE2008
Country/Territory	Portugal
City	Vilamoura
Period	08/4/14 → 08/4/16

All Science Journal Classification (ASJC) codes

Engineering(all)

Access to Document

10.1109/ISCE.2008.4559504

Cite this

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title = "A high performance motion vector processor IP design for H.264/AVC",

abstract = "In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 × 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 × 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.",

author = "Kiwon Yoo and Seungho Park and Hyunsuk Ko and Kwanghoon Sohn",

year = "2008",

doi = "10.1109/ISCE.2008.4559504",

language = "English",

isbn = "9781424424221",

series = "Proceedings of the International Symposium on Consumer Electronics, ISCE",

booktitle = "12th IEEE International Symposium on Consumer Electronics - ISCE2008",

note = "12th IEEE International Symposium on Consumer Electronics - ISCE2008 ; Conference date: 14-04-2008 Through 16-04-2008",

}

Yoo, K, Park, S, Ko, H & Sohn, K 2008, A high performance motion vector processor IP design for H.264/AVC. in 12th IEEE International Symposium on Consumer Electronics - ISCE2008., 4559504, Proceedings of the International Symposium on Consumer Electronics, ISCE, 12th IEEE International Symposium on Consumer Electronics - ISCE2008, Vilamoura, Portugal, 08/4/14. https://doi.org/10.1109/ISCE.2008.4559504

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T1 - A high performance motion vector processor IP design for H.264/AVC

AU - Yoo, Kiwon

AU - Park, Seungho

AU - Ko, Hyunsuk

AU - Sohn, Kwanghoon

PY - 2008

Y1 - 2008

N2 - In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 × 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 × 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.

AB - In this paper, the world's first hardware design of the motion vector processor of H.264/AVC and its FPGA implementation are presented. It aims at a low-cost high-throughput design for HD1080 (1920 × 1088) at 60 frames per second (fps) in High Profile (HP) H.264/AVC codec with Level 4.2. For this, deterministic processing loops control scheme and a novel 4 × 4 processing order substituting for the conventional double-Z one are presented to attain a high-throughput design. In addition, for maximizing hardware utilization and getting a low-cost design, two processing elements dedicated to motion vector derivation are presented. The proposed design was realized with 41 K logic gates and 4,608 bits SRAM at 266 MHz and was completely conformed for Allegro compliance bitstreams on an FPGA platform.

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DO - 10.1109/ISCE.2008.4559504

M3 - Conference contribution

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SN - 9781424424221

T3 - Proceedings of the International Symposium on Consumer Electronics, ISCE

BT - 12th IEEE International Symposium on Consumer Electronics - ISCE2008

T2 - 12th IEEE International Symposium on Consumer Electronics - ISCE2008

Y2 - 14 April 2008 through 16 April 2008

ER -

A high performance motion vector processor IP design for H.264/AVC

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