A high performance network-on-chip scheme using lossless data compression

Hong Sik Kim, Youngha Jung, Hyunjin Kim, Jin Ho Ahn, Woo Chan Park, Sungho Kang

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

A new NoC (network on chip) architecture using lossless data compression and decompression to improve the performance and power efficiency of the on-chip interconnect is proposed. In the proposed NoC scheme, the sender compresses the data to be transferred in order to reduce the number of data packets and the receiver decompresses the encoded data to restore the original data. For the lossless compression and decompression, we have implemented a hardware CODEC based on a Golomb-Rice algorithm. According to the experimental results using a cycle-accurate NoC simulator, the proposed scheme could significantly improve the performance and power efficiency of the conventional NoC architecture.

Original languageEnglish
Pages (from-to)791-796
Number of pages6
JournalIEICE Electronics Express
Volume7
Issue number11
DOIs
Publication statusPublished - 2010 Jun 10

Fingerprint

data compression
Data compression
chips
pressure reduction
power efficiency
rice
Simulators
simulators
Hardware
hardware
receivers
Network-on-chip
cycles

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Kim, Hong Sik ; Jung, Youngha ; Kim, Hyunjin ; Ahn, Jin Ho ; Park, Woo Chan ; Kang, Sungho. / A high performance network-on-chip scheme using lossless data compression. In: IEICE Electronics Express. 2010 ; Vol. 7, No. 11. pp. 791-796.
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A high performance network-on-chip scheme using lossless data compression. / Kim, Hong Sik; Jung, Youngha; Kim, Hyunjin; Ahn, Jin Ho; Park, Woo Chan; Kang, Sungho.

In: IEICE Electronics Express, Vol. 7, No. 11, 10.06.2010, p. 791-796.

Research output: Contribution to journalArticle

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