A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs

Seunghyun Lim, Jeonghwan Lee, Dongsoo Kim, Gunhee Han

Research output: Contribution to journalArticle

75 Citations (Scopus)

Abstract

This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 × 240 pixels has been fabricated with a 0.35-μm CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 μs, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

Original languageEnglish
Pages (from-to)393-398
Number of pages6
JournalIEEE Transactions on Electron Devices
Volume56
Issue number3
DOIs
Publication statusPublished - 2009 Mar 26

Fingerprint

Error correction
Image sensors
Electric power utilization
Pixels
Sensors
Electric potential

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Lim, Seunghyun ; Lee, Jeonghwan ; Kim, Dongsoo ; Han, Gunhee. / A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs. In: IEEE Transactions on Electron Devices. 2009 ; Vol. 56, No. 3. pp. 393-398.
@article{b49752c7978543aeb77fda1d1eebeecd,
title = "A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs",
abstract = "This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 × 240 pixels has been fabricated with a 0.35-μm CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 μs, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.",
author = "Seunghyun Lim and Jeonghwan Lee and Dongsoo Kim and Gunhee Han",
year = "2009",
month = "3",
day = "26",
doi = "10.1109/TED.2008.2011846",
language = "English",
volume = "56",
pages = "393--398",
journal = "IEEE Transactions on Electron Devices",
issn = "0018-9383",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs. / Lim, Seunghyun; Lee, Jeonghwan; Kim, Dongsoo; Han, Gunhee.

In: IEEE Transactions on Electron Devices, Vol. 56, No. 3, 26.03.2009, p. 393-398.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs

AU - Lim, Seunghyun

AU - Lee, Jeonghwan

AU - Kim, Dongsoo

AU - Han, Gunhee

PY - 2009/3/26

Y1 - 2009/3/26

N2 - This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 × 240 pixels has been fabricated with a 0.35-μm CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 μs, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

AB - This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 × 240 pixels has been fabricated with a 0.35-μm CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 μs, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

UR - http://www.scopus.com/inward/record.url?scp=62749178567&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=62749178567&partnerID=8YFLogxK

U2 - 10.1109/TED.2008.2011846

DO - 10.1109/TED.2008.2011846

M3 - Article

AN - SCOPUS:62749178567

VL - 56

SP - 393

EP - 398

JO - IEEE Transactions on Electron Devices

JF - IEEE Transactions on Electron Devices

SN - 0018-9383

IS - 3

ER -