A high-speed CMOS image sensor with column-parallel two-step single-slope ADCs

Seunghyun Lim, Jeonghwan Lee, Dongsoo Kim, Gunhee Han

Research output: Contribution to journalArticle

76 Citations (Scopus)


This paper proposes a column-parallel two-step single-slope (SS) ADC for high-speed CMOS image sensors. Error correction scheme to improve the linearity is proposed as well. A prototype sensor of 320 × 240 pixels has been fabricated with a 0.35-μm CMOS process. Measurement results demonstrate that the proposed ADC can achieve the conversion time of 4 μs, which is ten times faster than the conventional SS ADC. The proposed error correction effectively removes the dead band problem and yields DNL of +0.53/ -0.78 LSB and INL of +1.42/ -1.61 LSB. The power consumption is 36 mW from a supply voltage of 2.8 V.

Original languageEnglish
Pages (from-to)393-398
Number of pages6
JournalIEEE Transactions on Electron Devices
Issue number3
Publication statusPublished - 2009 Mar 26


All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

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