A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA

Hyun Yong Jung; Jeong Min Lee; Woo Young Choi

doi:10.1109/LPT.2015.2421501

A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA

Hyun Yong Jung, Jeong Min Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

15 Citations (Scopus)

Abstract

We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 2^31-1 PRBS and 12.5-Gb/s 2^7-1 PRBS operation with the bit-error rate less than 10^-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.

Original language	English
Article number	7086304
Pages (from-to)	1367-1370
Number of pages	4
Journal	IEEE Photonics Technology Letters
Volume	27
Issue number	13
DOIs	https://doi.org/10.1109/LPT.2015.2421501
Publication status	Published - 2015 Jul 1

Bibliographical note

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electronic, Optical and Magnetic Materials
Atomic and Molecular Physics, and Optics
Electrical and Electronic Engineering

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10.1109/LPT.2015.2421501

Cite this

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abstract = "We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.",

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A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA

Abstract

Bibliographical note

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