A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA

Hyun Yong Jung, Jeong Min Lee, Woo Young Choi

Research output: Contribution to journalArticle

12 Citations (Scopus)

Abstract

We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.

Original languageEnglish
Article number7086304
Pages (from-to)1367-1370
Number of pages4
JournalIEEE Photonics Technology Letters
Volume27
Issue number13
DOIs
Publication statusPublished - 2015 Jul 1

Fingerprint

Optical receivers
Operational amplifiers
Photodetectors
CMOS
Electric power utilization
receivers
amplifiers
high speed
Bandwidth
Bit error rate
avalanches
photometers
Buffers
bandwidth
Electric potential
bit error rate
buffers
output
sensitivity
electric potential

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Atomic and Molecular Physics, and Optics
  • Electrical and Electronic Engineering

Cite this

Jung, Hyun Yong ; Lee, Jeong Min ; Choi, Woo Young. / A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA. In: IEEE Photonics Technology Letters. 2015 ; Vol. 27, No. 13. pp. 1367-1370.
@article{d3137287ca5e4b9b9a973e5f6598d8be,
title = "A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA",
abstract = "We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.",
author = "Jung, {Hyun Yong} and Lee, {Jeong Min} and Choi, {Woo Young}",
year = "2015",
month = "7",
day = "1",
doi = "10.1109/LPT.2015.2421501",
language = "English",
volume = "27",
pages = "1367--1370",
journal = "IEEE Photonics Technology Letters",
issn = "1041-1135",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "13",

}

A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA. / Jung, Hyun Yong; Lee, Jeong Min; Choi, Woo Young.

In: IEEE Photonics Technology Letters, Vol. 27, No. 13, 7086304, 01.07.2015, p. 1367-1370.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA

AU - Jung, Hyun Yong

AU - Lee, Jeong Min

AU - Choi, Woo Young

PY - 2015/7/1

Y1 - 2015/7/1

N2 - We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.

AB - We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.

UR - http://www.scopus.com/inward/record.url?scp=84959340681&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84959340681&partnerID=8YFLogxK

U2 - 10.1109/LPT.2015.2421501

DO - 10.1109/LPT.2015.2421501

M3 - Article

VL - 27

SP - 1367

EP - 1370

JO - IEEE Photonics Technology Letters

JF - IEEE Photonics Technology Letters

SN - 1041-1135

IS - 13

M1 - 7086304

ER -