Abstract
We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.
| Original language | English |
|---|---|
| Article number | 7086304 |
| Pages (from-to) | 1367-1370 |
| Number of pages | 4 |
| Journal | IEEE Photonics Technology Letters |
| Volume | 27 |
| Issue number | 13 |
| DOIs | |
| Publication status | Published - 2015 Jul 1 |
Fingerprint
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Atomic and Molecular Physics, and Optics
- Electrical and Electronic Engineering
Cite this
}
A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA. / Jung, Hyun Yong; Lee, Jeong Min; Choi, Woo Young.
In: IEEE Photonics Technology Letters, Vol. 27, No. 13, 7086304, 01.07.2015, p. 1367-1370.Research output: Contribution to journal › Article
TY - JOUR
T1 - A High-Speed CMOS Integrated Optical Receiver with an Under-Damped TIA
AU - Jung, Hyun Yong
AU - Lee, Jeong Min
AU - Choi, Woo Young
PY - 2015/7/1
Y1 - 2015/7/1
N2 - We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.
AB - We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared with previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of-6 and-2 dBm, respectively. The receiver has core size of 0.24 mm × 0.1 mm and power consumption excluding output buffer of ∼ 13.7 mW with 1.2 V supply voltage.
UR - http://www.scopus.com/inward/record.url?scp=84959340681&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=84959340681&partnerID=8YFLogxK
U2 - 10.1109/LPT.2015.2421501
DO - 10.1109/LPT.2015.2421501
M3 - Article
AN - SCOPUS:84959340681
VL - 27
SP - 1367
EP - 1370
JO - IEEE Photonics Technology Letters
JF - IEEE Photonics Technology Letters
SN - 1041-1135
IS - 13
M1 - 7086304
ER -