A high-speed CMOS integrated optical receiver with an under-damped TIA

Hyun Yong Jung; Jeong Min Lee; Woo Young Choi

doi:10.1109/IPCon.2015.7323592

A high-speed CMOS integrated optical receiver with an under-damped TIA

Hyun Yong Jung, Jeong Min Lee, Woo Young Choi

Department of Electrical and Electronic Engineering

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

6 Citations (Scopus)

Abstract

We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared to previously reported techniques. We successfully demonstrate 10-Gb/s 2³¹-1 PRBS and 12.5-Gb/s 2⁷-1 PRBS operation with the bit-error rate less than 10^-12 at the incident optical power of -6 and -2 dBm, respectively. The receiver has core size of 0.24 × 0.1 mm² and power consumption excluding output buffer of about 13.7 mW with 1.2-V supply voltage.

Original language	English
Title of host publication	2015 IEEE Photonics Conference, IPC 2015
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	347-350
Number of pages	4
ISBN (Electronic)	9781479974658
DOIs	https://doi.org/10.1109/IPCon.2015.7323592
Publication status	Published - 2015 Nov 9
Event	IEEE Photonics Conference, IPC 2015 - Reston, United States Duration: 2015 Aug 30 → 2015 Aug 31

Publication series

Name	2015 IEEE Photonics Conference, IPC 2015

Other

Other	IEEE Photonics Conference, IPC 2015
Country/Territory	United States
City	Reston
Period	15/8/30 → 15/8/31

Bibliographical note

Funding Information:
This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (2012RIA2AIA-OI009233).

Publisher Copyright:
© 2015 IEEE.

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Access to Document

10.1109/IPCon.2015.7323592

Cite this

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title = "A high-speed CMOS integrated optical receiver with an under-damped TIA",

abstract = "We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared to previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of -6 and -2 dBm, respectively. The receiver has core size of 0.24 × 0.1 mm2 and power consumption excluding output buffer of about 13.7 mW with 1.2-V supply voltage.",

author = "Jung, {Hyun Yong} and Lee, {Jeong Min} and Choi, {Woo Young}",

note = "Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (2012RIA2AIA-OI009233). Publisher Copyright: {\textcopyright} 2015 IEEE.; IEEE Photonics Conference, IPC 2015 ; Conference date: 30-08-2015 Through 31-08-2015",

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doi = "10.1109/IPCon.2015.7323592",

language = "English",

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Jung, HY, Lee, JM & Choi, WY 2015, A high-speed CMOS integrated optical receiver with an under-damped TIA. in 2015 IEEE Photonics Conference, IPC 2015., 7323592, 2015 IEEE Photonics Conference, IPC 2015, Institute of Electrical and Electronics Engineers Inc., pp. 347-350, IEEE Photonics Conference, IPC 2015, Reston, United States, 15/8/30. https://doi.org/10.1109/IPCon.2015.7323592

A high-speed CMOS integrated optical receiver with an under-damped TIA. / Jung, Hyun Yong; Lee, Jeong Min; Choi, Woo Young.

2015 IEEE Photonics Conference, IPC 2015. Institute of Electrical and Electronics Engineers Inc., 2015. p. 347-350 7323592 (2015 IEEE Photonics Conference, IPC 2015).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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N1 - Funding Information: This work was supported by the National Research Foundation of Korea (NRF) grant funded by the Korea government (MEST) (2012RIA2AIA-OI009233). Publisher Copyright: © 2015 IEEE.

PY - 2015/11/9

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N2 - We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared to previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of -6 and -2 dBm, respectively. The receiver has core size of 0.24 × 0.1 mm2 and power consumption excluding output buffer of about 13.7 mW with 1.2-V supply voltage.

AB - We present a CMOS integrated optical receiver having under-damped transimpedance amplifier (TIA) and CMOS avalanche photodetector (APD) realized in 65-nm CMOS technology. The under-damped TIA compensates the bandwidth limitation of CMOS APD and provides enhanced receiver bandwidth performance with reduced power consumption and better sensitivity compared to previously reported techniques. We successfully demonstrate 10-Gb/s 231-1 PRBS and 12.5-Gb/s 27-1 PRBS operation with the bit-error rate less than 10-12 at the incident optical power of -6 and -2 dBm, respectively. The receiver has core size of 0.24 × 0.1 mm2 and power consumption excluding output buffer of about 13.7 mW with 1.2-V supply voltage.

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A high-speed CMOS integrated optical receiver with an under-damped TIA

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