A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk

Jung Wook Park, Seung Ho Park, Charles C. Weems, Shin-Dug Kim

Research output: Contribution to journalArticle

21 Citations (Scopus)

Abstract

This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.

Original languageEnglish
Pages (from-to)48-59
Number of pages12
JournalMicroprocessors and Microsystems
Volume35
Issue number1
DOIs
Publication statusPublished - 2011 Feb 1

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Flash memory
Durability
Data storage equipment
Costs

All Science Journal Classification (ASJC) codes

  • Software
  • Hardware and Architecture
  • Computer Networks and Communications
  • Artificial Intelligence

Cite this

Park, Jung Wook ; Park, Seung Ho ; Weems, Charles C. ; Kim, Shin-Dug. / A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk. In: Microprocessors and Microsystems. 2011 ; Vol. 35, No. 1. pp. 48-59.
@article{203eff57309d41a5aae6eb60cce10489,
title = "A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk",
abstract = "This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80{\%} MLC NAND and 20{\%} SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.",
author = "Park, {Jung Wook} and Park, {Seung Ho} and Weems, {Charles C.} and Shin-Dug Kim",
year = "2011",
month = "2",
day = "1",
doi = "10.1016/j.micpro.2010.08.001",
language = "English",
volume = "35",
pages = "48--59",
journal = "Microprocessors and Microsystems",
issn = "0141-9331",
publisher = "Elsevier",
number = "1",

}

A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk. / Park, Jung Wook; Park, Seung Ho; Weems, Charles C.; Kim, Shin-Dug.

In: Microprocessors and Microsystems, Vol. 35, No. 1, 01.02.2011, p. 48-59.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A hybrid flash translation layer design for SLC-MLC flash memory based multibank solid state disk

AU - Park, Jung Wook

AU - Park, Seung Ho

AU - Weems, Charles C.

AU - Kim, Shin-Dug

PY - 2011/2/1

Y1 - 2011/2/1

N2 - This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.

AB - This paper presents the design of a NAND flash based solid state disk (SSD), which can support various storage access patterns commonly observed in a PC environment. It is based on a hybrid model of high-performance SLC (single-level cell) NAND and low cost MLC (multi-level cell) NAND flash memories. Typically, SLC NAND has a higher transfer rate and greater cell endurance than MLC NAND flash memory. MLC NAND, on the other hand, benefits from lower price and higher capacity. In order to achieve higher performance than traditional SSDs, an interleaving technique that places NAND flash chips in parallel is essential. However, using the traditional FTL (flash translation layer) on an SSD with only MLC NAND chips is inefficient because the size of a logical block becomes large as the mapping address unit grows. In this paper, we proposed a HFTL (hybrid flash translation layer) which makes use of chained-blocks, combining SLC NAND and MLC NAND flash memories in parallel. Experimental results show that for most of the traces studied, the HFTL in an SSD configuration composed of 80% MLC NAND and 20% SLC NAND memories can improve performance compared to other solid state disk configurations, composed of either SLC NAND or MLC NAND flash memory alone.

UR - http://www.scopus.com/inward/record.url?scp=79551499873&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=79551499873&partnerID=8YFLogxK

U2 - 10.1016/j.micpro.2010.08.001

DO - 10.1016/j.micpro.2010.08.001

M3 - Article

AN - SCOPUS:79551499873

VL - 35

SP - 48

EP - 59

JO - Microprocessors and Microsystems

JF - Microprocessors and Microsystems

SN - 0141-9331

IS - 1

ER -