A low-cost DDEM ADC structure for the testing of high-performance DACs

Jaewon Jang, Incheol Kim, Hyeonuk Son, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

1 Citation (Scopus)

Abstract

The testing of high resolution and high speed DACs (Digital-to-Analog Converters) is extremely challenging because of the requirements on the accuracy, speed and cost. This paper presents a new hardware overhead reduction method using DDEM (Deterministic Dynamic Element Matching) techniques for the testing of DACs. In this work, the proposed method make that resistors in a resistor string have different lengths by a merging operation. Accuracy of the proposed method is proven by theoretical analysis. The experimental results show that the proposed method reduces the usage of resources over 17%.

Original languageEnglish
Title of host publication54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
DOIs
Publication statusPublished - 2011 Oct 13
Event54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 - Seoul, Korea, Republic of
Duration: 2011 Aug 72011 Aug 10

Other

Other54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011
CountryKorea, Republic of
CitySeoul
Period11/8/711/8/10

Fingerprint

Digital to analog conversion
Resistors
Testing
Merging
Costs
Hardware

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

Cite this

Jang, J., Kim, I., Son, H., & Kang, S. (2011). A low-cost DDEM ADC structure for the testing of high-performance DACs. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011 [6026360] https://doi.org/10.1109/MWSCAS.2011.6026360
Jang, Jaewon ; Kim, Incheol ; Son, Hyeonuk ; Kang, Sungho. / A low-cost DDEM ADC structure for the testing of high-performance DACs. 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011.
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Jang, J, Kim, I, Son, H & Kang, S 2011, A low-cost DDEM ADC structure for the testing of high-performance DACs. in 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011., 6026360, 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011, Seoul, Korea, Republic of, 11/8/7. https://doi.org/10.1109/MWSCAS.2011.6026360

A low-cost DDEM ADC structure for the testing of high-performance DACs. / Jang, Jaewon; Kim, Incheol; Son, Hyeonuk; Kang, Sungho.

54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026360.

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jang J, Kim I, Son H, Kang S. A low-cost DDEM ADC structure for the testing of high-performance DACs. In 54th IEEE International Midwest Symposium on Circuits and Systems, MWSCAS 2011. 2011. 6026360 https://doi.org/10.1109/MWSCAS.2011.6026360