A low noise and low power CMOS image sensor with pixel-level correlated double sampling

Dongsoo Kim, Gunhee Han

Research output: Chapter in Book/Report/Conference proceedingConference contribution

4 Citations (Scopus)

Abstract

A Low noise and low power CMOS Image Sensor (CIS) with pixel-level Correlated Double Sampling (CDS) is proposed. As the pixel readout circuit using source follower is major readout noise and power consumption source in the conventional CIS structure, the proposed new structure removes the source follower and performs pixel-level CDS and comparing. The proposed CIS is integrated with 240×180 pixel array. A pixel fill factor is 32% and its pitch is 8.4μm. The test chip was fabricated with CMOS 0.35-μm process and its power consumption is 18 mW with 3.3 V occupying 8.1 mm2

Original languageEnglish
Title of host publicationProceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
Pages113-115
Number of pages3
DOIs
Publication statusPublished - 2007 Dec 1
Event2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS - Krakow, Poland
Duration: 2007 Apr 112007 Apr 13

Publication series

NameProceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS

Other

Other2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS
CountryPoland
CityKrakow
Period07/4/1107/4/13

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Electrical and Electronic Engineering

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    Kim, D., & Han, G. (2007). A low noise and low power CMOS image sensor with pixel-level correlated double sampling. In Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS (pp. 113-115). [4295263] (Proceedings of the 2007 IEEE Workshop on Design and Diagnostics of Electronic Circuits and Systems, DDECS). https://doi.org/10.1109/DDECS.2007.4295263