We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35um 1P4M CMOS technology and is 32.4% faster than the adder using All-N-Transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35um CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.
|Journal||Proceedings - IEEE International Symposium on Circuits and Systems|
|Publication status||Published - 2004|
|Event||2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada|
Duration: 2004 May 23 → 2004 May 26
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering