A low-power 1.85 GHZ 32-bit carry lookahead adder using Dual Path All-N-Logic

Ge Yang; Seong Ook Jung; Kwang Hyun Baek; Soo Hwan Kim; Suki Kim; Sung Mo Kang

A low-power 1.85 GHZ 32-bit carry lookahead adder using Dual Path All-N-Logic

Ge Yang, Seong Ook Jung, Kwang Hyun Baek, Soo Hwan Kim, Suki Kim, Sung Mo Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Conference article › peer-review

5 Citations (Scopus)

Abstract

We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35um 1P4M CMOS technology and is 32.4% faster than the adder using All-N-Transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35um CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Original language	English
Pages (from-to)	II781-II784
Journal	Proceedings - IEEE International Symposium on Circuits and Systems
Volume	2
Publication status	Published - 2004
Event	2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada Duration: 2004 May 23 → 2004 May 26

All Science Journal Classification (ASJC) codes

Electrical and Electronic Engineering

Cite this

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title = "A low-power 1.85 GHZ 32-bit carry lookahead adder using Dual Path All-N-Logic",

abstract = "We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35um 1P4M CMOS technology and is 32.4% faster than the adder using All-N-Transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35um CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.",

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T1 - A low-power 1.85 GHZ 32-bit carry lookahead adder using Dual Path All-N-Logic

AU - Yang, Ge

AU - Jung, Seong Ook

AU - Baek, Kwang Hyun

AU - Kim, Soo Hwan

AU - Kim, Suki

AU - Kang, Sung Mo

PY - 2004

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N2 - We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35um 1P4M CMOS technology and is 32.4% faster than the adder using All-N-Transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35um CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

AB - We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35um 1P4M CMOS technology and is 32.4% faster than the adder using All-N-Transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35um CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

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JO - Proceedings - IEEE International Symposium on Circuits and Systems

JF - Proceedings - IEEE International Symposium on Circuits and Systems

T2 - 2004 IEEE International Symposium on Circuits and Systems - Proceedings

Y2 - 23 May 2004 through 26 May 2004

ER -

A low-power 1.85 GHZ 32-bit carry lookahead adder using Dual Path All-N-Logic

Abstract

All Science Journal Classification (ASJC) codes

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