A low-power 1.85 GHZ 32-bit carry lookahead adder using Dual Path All-N-Logic

Ge Yang, Seong Ook Jung, Kwang Hyun Baek, Soo Hwan Kim, Suki Kim, Sung Mo Kang

Research output: Contribution to journalConference article

5 Citations (Scopus)


We have developed Dual Path All-N-Logic (DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. Post-layout simulation results show that this adder can operate at frequencies up to 1.85 GHz for 0.35um 1P4M CMOS technology and is 32.4% faster than the adder using All-N-Transistor (ANT). It also consumes 29.2% less power than the ANT adder. A 0.35um CMOS chip has been fabricated and tested to verify the functionality and performance of the DPANL adder on silicon.

Original languageEnglish
Pages (from-to)II781-II784
JournalProceedings - IEEE International Symposium on Circuits and Systems
Publication statusPublished - 2004 Sep 7
Event2004 IEEE International Symposium on Circuits and Systems - Proceedings - Vancouver, BC, Canada
Duration: 2004 May 232004 May 26


All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

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