A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic

Ge Yang, Seong Ook Jung, Soo Hwan Kim, Sung Mo Kang

Research output: Contribution to conferencePaper

4 Citations (Scopus)

Abstract

A high-speed, low-power 32-bit carry lookahead adder is presented. We have developed Dual Path All-N-Logic(DPANL) and applied to 32-bit adder design for higher performance. The speed enhancement is mainly due to reduced capacitance at each evaluation node of dynamic circuits. This adder can operate at frequencies up to 2.1 GHz for 0.35um 1P4M CMOS technology and is 31.3% and 27.3% faster than the adders using All-N-Transistor(ANT) and All-N-Logic(ANL), respectively. It also consumes 29.2% and 15.4% less power than the ANT adder and ANL adder, respectively.

Original languageEnglish
PagesII298-II301
Publication statusPublished - 2002 Dec 1
Event2002 45th Midwest Symposium on Circuits and Systems - Tulsa, OK, United States
Duration: 2002 Aug 42002 Aug 7

Other

Other2002 45th Midwest Symposium on Circuits and Systems
CountryUnited States
CityTulsa, OK
Period02/8/402/8/7

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All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Yang, G., Jung, S. O., Kim, S. H., & Kang, S. M. (2002). A low-power 2.1 GHz 32-bit carry lookahead adder using dual path All-N-Logic. II298-II301. Paper presented at 2002 45th Midwest Symposium on Circuits and Systems, Tulsa, OK, United States.