A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction

Dong Hoon Jung, Kyungho Ryu, Jung Hyun Park, Seong Ook Jung

Research output: Chapter in Book/Report/Conference proceedingConference contribution

8 Citations (Scopus)

Abstract

In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm2. The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8% and 1.04% for an input duty cycle from 30% to 70% and the power consumption of the proposed DLL is 3.84 mW.

Original languageEnglish
Title of host publication2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012
Pages181-184
Number of pages4
DOIs
Publication statusPublished - 2012 Dec 14
Event38th European Solid State Circuits Conference, ESSCIRC 2012 - Bordeaux, France
Duration: 2012 Sep 172012 Sep 21

Publication series

NameEuropean Solid-State Circuits Conference
ISSN (Print)1930-8833

Other

Other38th European Solid State Circuits Conference, ESSCIRC 2012
CountryFrance
CityBordeaux
Period12/9/1712/9/21

Fingerprint

Electric power utilization
Networks (circuits)
Electric delay lines
Electric potential

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Jung, D. H., Ryu, K., Park, J. H., & Jung, S. O. (2012). A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. In 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012 (pp. 181-184). [6341288] (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2012.6341288
Jung, Dong Hoon ; Ryu, Kyungho ; Park, Jung Hyun ; Jung, Seong Ook. / A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. pp. 181-184 (European Solid-State Circuits Conference).
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abstract = "In this paper, we propose a delay-locked loop (DLL) with a closed-loop duty-cycle correction (DCC) circuit. The proposed DCC circuit does not require additional blocks for DCC, and this enables it to have a significantly reduced power consumption and area. To increase DCC accuracy, we also propose a duty cycle keeping fine delay line. The proposed DLL is implemented using a 0.13 μm process with a supply voltage of 1.2 V. The active chip area is 0.02 mm2. The operating frequency range of the proposed DLL is from 400 MHz to 800 MHz. At all operating frequencies, the proposed DLL achieves an output duty-cycle error between -0.8{\%} and 1.04{\%} for an input duty cycle from 30{\%} to 70{\%} and the power consumption of the proposed DLL is 3.84 mW.",
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Jung, DH, Ryu, K, Park, JH & Jung, SO 2012, A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. in 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012., 6341288, European Solid-State Circuits Conference, pp. 181-184, 38th European Solid State Circuits Conference, ESSCIRC 2012, Bordeaux, France, 12/9/17. https://doi.org/10.1109/ESSCIRC.2012.6341288

A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. / Jung, Dong Hoon; Ryu, Kyungho; Park, Jung Hyun; Jung, Seong Ook.

2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 181-184 6341288 (European Solid-State Circuits Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Jung DH, Ryu K, Park JH, Jung SO. A low-power and small-area all-digital delay-locked loop with closed-loop duty-cycle correction. In 2012 Proceedings of the European Solid State Circuits Conference, ESSCIRC 2012. 2012. p. 181-184. 6341288. (European Solid-State Circuits Conference). https://doi.org/10.1109/ESSCIRC.2012.6341288