A low-power cache system for embedded processors

Gi Ho Park, Kil Whan Lee, Jang Soo Lee, Tack-Don Han, Shin-Dug Kim, Yong Chun Kim, Seh Woong Jeong, Kwang Yup Lee

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

Original languageEnglish
Pages (from-to)316-319
Number of pages4
JournalMidwest Symposium on Circuits and Systems
Volume1
DOIs
Publication statusPublished - 2000 Jan 1

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Electric power utilization
Electronic equipment
Metals

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Park, Gi Ho ; Lee, Kil Whan ; Lee, Jang Soo ; Han, Tack-Don ; Kim, Shin-Dug ; Kim, Yong Chun ; Jeong, Seh Woong ; Lee, Kwang Yup. / A low-power cache system for embedded processors. In: Midwest Symposium on Circuits and Systems. 2000 ; Vol. 1. pp. 316-319.
@article{1939fde216434683a98fad181d0ab802,
title = "A low-power cache system for embedded processors",
abstract = "A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.",
author = "Park, {Gi Ho} and Lee, {Kil Whan} and Lee, {Jang Soo} and Tack-Don Han and Shin-Dug Kim and Kim, {Yong Chun} and Jeong, {Seh Woong} and Lee, {Kwang Yup}",
year = "2000",
month = "1",
day = "1",
doi = "10.1109/MWSCAS.2000.951650",
language = "English",
volume = "1",
pages = "316--319",
journal = "Midwest Symposium on Circuits and Systems",
issn = "1548-3746",
publisher = "Institute of Electrical and Electronics Engineers Inc.",

}

A low-power cache system for embedded processors. / Park, Gi Ho; Lee, Kil Whan; Lee, Jang Soo; Han, Tack-Don; Kim, Shin-Dug; Kim, Yong Chun; Jeong, Seh Woong; Lee, Kwang Yup.

In: Midwest Symposium on Circuits and Systems, Vol. 1, 01.01.2000, p. 316-319.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A low-power cache system for embedded processors

AU - Park, Gi Ho

AU - Lee, Kil Whan

AU - Lee, Jang Soo

AU - Han, Tack-Don

AU - Kim, Shin-Dug

AU - Kim, Yong Chun

AU - Jeong, Seh Woong

AU - Lee, Kwang Yup

PY - 2000/1/1

Y1 - 2000/1/1

N2 - A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

AB - A low-power cache structure for embedded processors, called a cooperative cache system, is presented in this paper. The cooperative cache system reduces power consumption of the cache system by virtue of the structural characteristics that consists of two separate caches having different associativities and block sizes. The cooperative cache system is adopted as the cache structure for the CalmRISC-32 embedded processor that the prototype chip of it is recently manufactured with 0.25μm, 4-metal process by Samsung Electronics Co.

UR - http://www.scopus.com/inward/record.url?scp=0034465912&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=0034465912&partnerID=8YFLogxK

U2 - 10.1109/MWSCAS.2000.951650

DO - 10.1109/MWSCAS.2000.951650

M3 - Article

AN - SCOPUS:0034465912

VL - 1

SP - 316

EP - 319

JO - Midwest Symposium on Circuits and Systems

JF - Midwest Symposium on Circuits and Systems

SN - 1548-3746

ER -