A low power CMOS adaptive line equalizer for fast Ethernet

Kwisung Yoo, Hoon Lee, Gunhee Han

Research output: Chapter in Book/Report/Conference proceedingConference contribution

5 Citations (Scopus)

Abstract

An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 μm CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm2).

Original languageEnglish
Title of host publication2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages129-132
Number of pages4
ISBN (Electronic)0780373634, 9780780373631
DOIs
Publication statusPublished - 2002 Jan 1
Event3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan, Province of China
Duration: 2002 Aug 62002 Aug 8

Publication series

Name2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
CountryTaiwan, Province of China
CityTaipei
Period02/8/602/8/8

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All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering

Cite this

Yoo, K., Lee, H., & Han, G. (2002). A low power CMOS adaptive line equalizer for fast Ethernet. In 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings (pp. 129-132). [1031549] (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.2002.1031549