A low power CMOS adaptive line equalizer for fast Ethernet

Kwisung Yoo; Hoon Lee; Gunhee Han

doi:10.1109/APASIC.2002.1031549

A low power CMOS adaptive line equalizer for fast Ethernet

Kwisung Yoo, Hoon Lee, Gunhee Han

School of Integrated Technology

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

5 Citations (Scopus)

Abstract

An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 μm CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm²).

Original language	English
Title of host publication	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings
Publisher	Institute of Electrical and Electronics Engineers Inc.
Pages	129-132
Number of pages	4
ISBN (Electronic)	0780373634, 9780780373631
DOIs	https://doi.org/10.1109/APASIC.2002.1031549
Publication status	Published - 2002
Event	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Taipei, Taiwan, Province of China Duration: 2002 Aug 6 → 2002 Aug 8

Publication series

Name	2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings

Other

Other	3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002
Country/Territory	Taiwan, Province of China
City	Taipei
Period	02/8/6 → 02/8/8

Bibliographical note

Publisher Copyright:
© 2002 IEEE.

All Science Journal Classification (ASJC) codes

Hardware and Architecture
Electrical and Electronic Engineering

Access to Document

10.1109/APASIC.2002.1031549

Cite this

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title = "A low power CMOS adaptive line equalizer for fast Ethernet",

abstract = "An analog adaptive line equalizer has been developed for 155 Mbps fast Ethernet data communication up to 100 m UTP (unshielded twisted pair) cable. The proposed adaptive equalizer is designed for the 0.35 μm CMOS process. The designed equalizer has low power consumption (19 mW) and small silicon area (0.07 mm2).",

author = "Kwisung Yoo and Hoon Lee and Gunhee Han",

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doi = "10.1109/APASIC.2002.1031549",

language = "English",

series = "2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings",

publisher = "Institute of Electrical and Electronics Engineers Inc.",

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Yoo, K, Lee, H & Han, G 2002, A low power CMOS adaptive line equalizer for fast Ethernet. in 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings., 1031549, 2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings, Institute of Electrical and Electronics Engineers Inc., pp. 129-132, 3rd IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002, Taipei, Taiwan, Province of China, 02/8/6. https://doi.org/10.1109/APASIC.2002.1031549

A low power CMOS adaptive line equalizer for fast Ethernet. / Yoo, Kwisung; Lee, Hoon; Han, Gunhee.

2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings. Institute of Electrical and Electronics Engineers Inc., 2002. p. 129-132 1031549 (2002 IEEE Asia-Pacific Conference on ASIC, AP-ASIC 2002 - Proceedings).

Research output: Chapter in Book/Report/Conference proceeding › Conference contribution

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A low power CMOS adaptive line equalizer for fast Ethernet

Abstract

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Bibliographical note

All Science Journal Classification (ASJC) codes

Access to Document

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