A low power through-silicon via (TSV) I/O for the high-bandwidth memory is proposed with a 65nm CMOS process. The proposed TSV I/O, which employs a low-supply voltage for low-power operation, consists of a 4-to-1 multiplexer (MUX) with replica MUX, pre-driver that realizes pre-emphasis without static power consumption, and digitally calibrated 1-to-4 de-MUX comparator. The measured energy efficiency is 0.179-0.185pJ/b/pF with a PRBS-31 at 5-10Gb/s.
|Title of host publication||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2022|
|Event||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022 - Honolulu, United States|
Duration: 2022 Jun 12 → 2022 Jun 17
|Name||Digest of Technical Papers - Symposium on VLSI Technology|
|Conference||2022 IEEE Symposium on VLSI Technology and Circuits, VLSI Technology and Circuits 2022|
|Period||22/6/12 → 22/6/17|
Bibliographical noteFunding Information:
This work was supported by Samsung Electronics Company, Ltd.
© 2022 IEEE.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering