A low-voltage PLL with a current mismatch compensated charge pump

Sung Geun Kim, Jinsoo Rhim, Dae Hyun Kwon, Min Hyeong Kim, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

A low-voltage phase-locked loop (PLL) circuit having a charge pump (CP) with a novel negative feedback replica bias scheme for current mismatch compensation is demonstrated. A prototype 400-MHz PLL circuit operating at 0.65-V is fabricated with 180-nm standard CMOS process. Measurement results show that current mismatch compensation is successfully achieved. Our PLL consumes only 140-μW.

Original languageEnglish
Title of host publicationISOCC 2015 - International SoC Design Conference
Subtitle of host publicationSoC for Internet of Everything (IoE)
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages15-16
Number of pages2
ISBN (Electronic)9781467393089
DOIs
Publication statusPublished - 2016 Feb 8
Event12th International SoC Design Conference, ISOCC 2015 - Gyeongju, Korea, Republic of
Duration: 2015 Nov 22015 Nov 5

Publication series

NameISOCC 2015 - International SoC Design Conference: SoC for Internet of Everything (IoE)

Other

Other12th International SoC Design Conference, ISOCC 2015
CountryKorea, Republic of
CityGyeongju
Period15/11/215/11/5

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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