A memory access system for merged memory with logic LSIs

Youngsik Kim, Tack Don Han, Shin Dug Kim

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

This paper proposes a new memory access control scheme called delayed precharge scheme, to improve the performance of on-chip DRAM's by increasing the DRAM page hit ratio for multiple block accesses. This architecture shows higher performance than the hierarchical multi-bank architecture as well as the conventional bank architecture by execution-driven simulation. The proposed scheme could reduce the cache refill time and CPI obtained by the conventional DRAM by 26.9% and 6.2% respectively in typical applications.

Original languageEnglish
Title of host publicationAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages384-387
Number of pages4
ISBN (Print)0780357051, 9780780357051
DOIs
Publication statusPublished - 1999 Jan 1
Event1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999 - Seoul, Korea, Republic of
Duration: 1999 Aug 231999 Aug 25

Publication series

NameAP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs

Other

Other1st IEEE Asia Pacific Conference on ASICs, AP-ASIC 1999
CountryKorea, Republic of
CitySeoul
Period99/8/2399/8/25

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Safety, Risk, Reliability and Quality
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Kim, Y., Han, T. D., & Kim, S. D. (1999). A memory access system for merged memory with logic LSIs. In AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs (pp. 384-387). [824114] (AP-ASIC 1999 - 1st IEEE Asia Pacific Conference on ASICs). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/APASIC.1999.824114