A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection

Hyunjin Kim, Hyejeong Hong, Dongmyoung Baek, Jin Ho Ahn, Sungho Kang

Research output: Contribution to journalArticle

5 Citations (Scopus)

Abstract

This paper presents for hardware-based parallel pattern matching scheme that adopts heterogeneous bit-split string matchers for deep packet inspection (DPI) devices. Considering the pattern lengths, a set of target patterns is partitioned into two subsets for short and long patterns. By adopting the appropriate bit-split string matcher types for the two subsets, the memory requirements can be optimized for the bit-split parallel pattern matching engine. Experimental results show that the total memory requirements decrease by 39.40% and 20.52%, in comparison with the existing bit-split pattern matching approaches.

Original languageEnglish
Pages (from-to)377-382
Number of pages6
Journalieice electronics express
Volume7
Issue number5
DOIs
Publication statusPublished - 2010 Mar 10

Fingerprint

Pattern matching
inspection
Inspection
Data storage equipment
set theory
strings
requirements
Engines
Hardware
engines
hardware

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Electrical and Electronic Engineering

Cite this

Kim, Hyunjin ; Hong, Hyejeong ; Baek, Dongmyoung ; Ahn, Jin Ho ; Kang, Sungho. / A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection. In: ieice electronics express. 2010 ; Vol. 7, No. 5. pp. 377-382.
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A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection. / Kim, Hyunjin; Hong, Hyejeong; Baek, Dongmyoung; Ahn, Jin Ho; Kang, Sungho.

In: ieice electronics express, Vol. 7, No. 5, 10.03.2010, p. 377-382.

Research output: Contribution to journalArticle

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