Abstract
This paper presents for hardware-based parallel pattern matching scheme that adopts heterogeneous bit-split string matchers for deep packet inspection (DPI) devices. Considering the pattern lengths, a set of target patterns is partitioned into two subsets for short and long patterns. By adopting the appropriate bit-split string matcher types for the two subsets, the memory requirements can be optimized for the bit-split parallel pattern matching engine. Experimental results show that the total memory requirements decrease by 39.40% and 20.52%, in comparison with the existing bit-split pattern matching approaches.
| Original language | English |
|---|---|
| Pages (from-to) | 377-382 |
| Number of pages | 6 |
| Journal | ieice electronics express |
| Volume | 7 |
| Issue number | 5 |
| DOIs | |
| Publication status | Published - 2010 Mar 10 |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Electrical and Electronic Engineering
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Cite this
Kim, H., Hong, H., Baek, D., Ahn, J. H., & Kang, S. (2010). A memory-efficient heterogeneous parallel pattern matching scheme in deep packet inspection. ieice electronics express, 7(5), 377-382. https://doi.org/10.1587/elex.7.377