A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection

Hyun Jin Kim, Hong Sik Kim, Jung Hee Lee, Jin Ho Ahn, Sungho Kang

Research output: Contribution to journalArticle

2 Citations (Scopus)

Abstract

This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.

Original languageEnglish
Pages (from-to)396-398
Number of pages3
JournalIEICE Transactions on Communications
VolumeE93-B
Issue number2
DOIs
Publication statusPublished - 2010 Jan 1

Fingerprint

Pattern matching
Computer hardware
Inspection
Data storage equipment
Engines

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

Kim, Hyun Jin ; Kim, Hong Sik ; Lee, Jung Hee ; Ahn, Jin Ho ; Kang, Sungho. / A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection. In: IEICE Transactions on Communications. 2010 ; Vol. E93-B, No. 2. pp. 396-398.
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A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection. / Kim, Hyun Jin; Kim, Hong Sik; Lee, Jung Hee; Ahn, Jin Ho; Kang, Sungho.

In: IEICE Transactions on Communications, Vol. E93-B, No. 2, 01.01.2010, p. 396-398.

Research output: Contribution to journalArticle

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