Abstract
This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.
| Original language | English |
|---|---|
| Pages (from-to) | 396-398 |
| Number of pages | 3 |
| Journal | IEICE Transactions on Communications |
| Volume | E93-B |
| Issue number | 2 |
| DOIs | |
| Publication status | Published - 2010 Jan 1 |
All Science Journal Classification (ASJC) codes
- Software
- Computer Networks and Communications
- Electrical and Electronic Engineering
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Cite this
Kim, H. J., Kim, H. S., Lee, J. H., Ahn, J. H., & Kang, S. (2010). A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection. IEICE Transactions on Communications, E93-B(2), 396-398. https://doi.org/10.1587/transcom.E93.B.396