Abstract
This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.
Original language | English |
---|---|
Pages (from-to) | 396-398 |
Number of pages | 3 |
Journal | IEICE Transactions on Communications |
Volume | E93-B |
Issue number | 2 |
DOIs | |
Publication status | Published - 2010 |
All Science Journal Classification (ASJC) codes
- Software
- Computer Networks and Communications
- Electrical and Electronic Engineering