A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection

Hyun Jin Kim; Hong Sik Kim; Jung Hee Lee; Jin Ho Ahn; Sungho Kang

doi:10.1587/transcom.E93.B.396

A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection

Hyun Jin Kim, Hong Sik Kim, Jung Hee Lee, Jin Ho Ahn, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

2 Citations (Scopus)

Abstract

This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.

Original language	English
Pages (from-to)	396-398
Number of pages	3
Journal	IEICE Transactions on Communications
Volume	E93-B
Issue number	2
DOIs	https://doi.org/10.1587/transcom.E93.B.396
Publication status	Published - 2010

All Science Journal Classification (ASJC) codes

Software
Computer Networks and Communications
Electrical and Electronic Engineering

Access to Document

10.1587/transcom.E93.B.396

Cite this

@article{e48d8fd3aa754a2ba5527e3763b8f850,

title = "A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection",

abstract = "This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.",

author = "Kim, {Hyun Jin} and Kim, {Hong Sik} and Lee, {Jung Hee} and Ahn, {Jin Ho} and Sungho Kang",

year = "2010",

doi = "10.1587/transcom.E93.B.396",

language = "English",

volume = "E93-B",

pages = "396--398",

journal = "IEICE Transactions on Communications",

issn = "0916-8516",

publisher = "Maruzen Co., Ltd/Maruzen Kabushikikaisha",

number = "2",

}

TY - JOUR

T1 - A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection

AU - Kim, Hyun Jin

AU - Kim, Hong Sik

AU - Lee, Jung Hee

AU - Ahn, Jin Ho

AU - Kang, Sungho

PY - 2010

Y1 - 2010

N2 - This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.

AB - This paper proposes a hardware-based parallel pattern matching engine using a memory-based bit-split string matcher architecture. The proposed bit-split string matcher separates the transition table from the state table, so that state transitions towards the initial state are not stored. Therefore total memory requirements can be minimized.

UR - http://www.scopus.com/inward/record.url?scp=77950511054&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=77950511054&partnerID=8YFLogxK

U2 - 10.1587/transcom.E93.B.396

DO - 10.1587/transcom.E93.B.396

M3 - Article

AN - SCOPUS:77950511054

VL - E93-B

SP - 396

EP - 398

JO - IEICE Transactions on Communications

JF - IEICE Transactions on Communications

SN - 0916-8516

IS - 2

ER -

A memory-efficient pattern matching with hardware-based bit-split string matchers for deep packet inspection

Abstract

All Science Journal Classification (ASJC) codes

Access to Document

Other files and links

Fingerprint

Cite this