A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors

Woo Chen Park, Kil Whan Lee, Il San Kim, Tack-Don Han, Sung-Bong Yang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

2 Citations (Scopus)

Abstract

As a 3D scene becomes increasingly complex and the screen resolution increases, the design of effective memory architecture is one of the most important issues for 3D rendering processors. We propose a pixel rasterization architecture, which performs a depth test operation twice, before and after texture mapping. The proposed architecture eliminates memory bandwidth waste caused by fetching unnecessary obscured texture data, by performing the depth test before texture mapping. The proposed architecture reduces the miss penalties of the pixel cache by using a pre-fetch scheme - that is, a frame memory access, due to a cache miss at the first depth test, is done simultaneously with texture mapping. The proposed pixel rasterization architecture achieves memory bandwidth effectiveness and reduces power consumption, producing high-performance gains.

Original languageEnglish
Title of host publicationProceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
EditorsRobert Schreiber, Shuvra Bhattacharyya, Neil Burgess, Michael Schulte
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages173-182
Number of pages10
ISBN (Electronic)0769517129
DOIs
Publication statusPublished - 2002 Jan 1
EventIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 - San Jose, United States
Duration: 2002 Jul 172002 Jul 19

Publication series

NameProceedings of the International Conference on Application-Specific Systems, Architectures and Processors
Volume2002-January
ISSN (Print)1063-6862

Other

OtherIEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002
CountryUnited States
CitySan Jose
Period02/7/1702/7/19

Fingerprint

Texturing
Memory architecture
Pipelines
Textures
Pixels
Bandwidth
Electric power utilization
Data storage equipment
Rendering (computer graphics)
Rasterization

All Science Journal Classification (ASJC) codes

  • Hardware and Architecture
  • Computer Networks and Communications

Cite this

Park, W. C., Lee, K. W., Kim, I. S., Han, T-D., & Yang, S-B. (2002). A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. In R. Schreiber, S. Bhattacharyya, N. Burgess, & M. Schulte (Eds.), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002 (pp. 173-182). [1030717] (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2002-January). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ASAP.2002.1030717
Park, Woo Chen ; Lee, Kil Whan ; Kim, Il San ; Han, Tack-Don ; Yang, Sung-Bong. / A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002. editor / Robert Schreiber ; Shuvra Bhattacharyya ; Neil Burgess ; Michael Schulte. Institute of Electrical and Electronics Engineers Inc., 2002. pp. 173-182 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors).
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Park, WC, Lee, KW, Kim, IS, Han, T-D & Yang, S-B 2002, A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. in R Schreiber, S Bhattacharyya, N Burgess & M Schulte (eds), Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002., 1030717, Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors, vol. 2002-January, Institute of Electrical and Electronics Engineers Inc., pp. 173-182, IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002, San Jose, United States, 02/7/17. https://doi.org/10.1109/ASAP.2002.1030717

A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. / Park, Woo Chen; Lee, Kil Whan; Kim, Il San; Han, Tack-Don; Yang, Sung-Bong.

Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002. ed. / Robert Schreiber; Shuvra Bhattacharyya; Neil Burgess; Michael Schulte. Institute of Electrical and Electronics Engineers Inc., 2002. p. 173-182 1030717 (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors; Vol. 2002-January).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Park WC, Lee KW, Kim IS, Han T-D, Yang S-B. A mid-texturing pixel rasterization pipeline architecture for 3D rendering processors. In Schreiber R, Bhattacharyya S, Burgess N, Schulte M, editors, Proceedings - IEEE International Conference on Application-Specific Systems, Architectures, and Processors, ASAP 2002. Institute of Electrical and Electronics Engineers Inc. 2002. p. 173-182. 1030717. (Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors). https://doi.org/10.1109/ASAP.2002.1030717