We present a multi-band orthogonal frequency division multiplexing (MB-OFDM) ultrawideband (UWB) system on chip (SoC) for high speed wireless communications. The UWB SoC has a power management scheme to minimize the average power consumption and adopts hardware-efficient parallel processing architecture to reduce the logic gate count of the modem. Specifically, symbol synchronization block is implemented with the signed algorithm; automatic gain control (AGC), carrier frequency offset (CFO) estimation, and preamble delimitation check block share the eight complex multipliers during preamble transmission; and AGC, fast Fourier transform (FFT), symbol synchronization, CFO estimation, and preamble delimitation check blocks share the buffer which contains received symbols. This SoC adopts a 32-bit reduced instruction set computer (RISC) processor for high speed data transaction and supports universal serial bus (USB) 2.0 and secure digital input/output (SDIO) for host interface. The designed SoC is implemented with 90 nm CMOS technology with a core voltage of 1.2 V. The implemented chip size is about 5 mm x 5 mm1.
All Science Journal Classification (ASJC) codes
- Media Technology
- Electrical and Electronic Engineering