A negative charge pump using enhanced pumping clock for low-voltage DRAM

Choongkeun Lee, Taegun Yim, Hongil Yoon

Research output: Contribution to journalArticlepeer-review

2 Citations (Scopus)

Abstract

As the supply voltage decreases, there is a need for a high-speed negative charge pump circuit, for example, to produce the back-bias voltage (VBB) with high pumping efficiency at a low supply voltage (VDD). Beyond the basic negative charge pump circuit with the small area overhead, advanced schemes such as hybrid pump circuit (HCP) and cross-coupled hybrid pump circuits (CHPC) were introduced to improve the pumping efficiency and pump down speed. However, they still suffer from pumping efficiency degradation, low level |VBB|, and small pumping currents at very low VDD. A novel negative charge pump using an enhanced pumping clock is proposed. The proposed cross-coupled charge pump consists of the enhanced pumping clock generator (ECG) having a pair of inverters and PMOS latch circuit to produce an enhanced control signal with a greater amplitude, thereby working efficiently especially at low supply voltages. The proposed scheme is validated with a HSPICE simulation using the TSMC 180 nm process. The proposed scheme can be operated down to VDD = 0.4 V, and |VBB|/VDD is obtained to be 86.1% at VDD = 0.5 V and Cload = 20 nF. Compared to the state-of-the-art CHPC scheme, the pumping efficiency is larger by 35% at VDD = 0.6 V and RL = 10 KΩ, and the pumping current is 2.17 times greater at VDD = 1.2 V and VBB = 0 V, making the circuit suitable for very low supply voltage applications in DRAMs.

Original languageEnglish
Article number1769
Pages (from-to)1-11
Number of pages11
JournalElectronics (Switzerland)
Volume9
Issue number11
DOIs
Publication statusPublished - 2020 Nov

Bibliographical note

Funding Information:
Funding: This work was supported by the Technology Innovation Program (10080722, Integrated Server on Chip System Research for Cloud Computing) funded By the Ministry of Trade, industry & Energy (MI, Korea).

Funding Information:
Acknowledgments: This work was in part supported by Samsung Electronics, and the EDA tools were supported by the IC Design Education Center (IDEC).

Publisher Copyright:
© 2020 by the authors. Licensee MDPI, Basel, Switzerland.

All Science Journal Classification (ASJC) codes

  • Control and Systems Engineering
  • Signal Processing
  • Hardware and Architecture
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

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