A new 1.25-Gb/s burst mode clock and data recovery circuit using two digital phase aligners and a phase interpolator

Chang Kyung Seong, Seung Woo Lee, Woo Young Choi

Research output: Contribution to journalArticle

Abstract

We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30% and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-m CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231 - 1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.

Original languageEnglish
Pages (from-to)1397-1402
Number of pages6
JournalIEICE Transactions on Communications
VolumeE91-B
Issue number5
DOIs
Publication statusPublished - 2008 Jan 1

Fingerprint

Clock and data recovery circuits (CDR circuits)
Clocks
Jitter
Recovery

All Science Journal Classification (ASJC) codes

  • Software
  • Computer Networks and Communications
  • Electrical and Electronic Engineering

Cite this

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abstract = "We propose a new Clock and Data Recovery (CDR) circuit for burst-mode applications. It can recover clock signals after two data transitions and endure long sequence of consecutive identical digits. Two Digital Phase Aligners (DPAs), triggered by rising or falling edges of input data, recover clock signals, which are then combined by a phase interpolator. This configuration reduces the RMS jitters of the recovered clock by 30{\%} and doubles the maximum run length compared to a previously reported DPA CDR. A prototype chip is demonstrated with 0.18-m CMOS technology. Measurement results show that the chip operates without any bit error for 1.25-Gb/s 231 - 1 PRBS with 200-ppm frequency offset and recovers clock and data after two clock cycles.",
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A new 1.25-Gb/s burst mode clock and data recovery circuit using two digital phase aligners and a phase interpolator. / Seong, Chang Kyung; Lee, Seung Woo; Choi, Woo Young.

In: IEICE Transactions on Communications, Vol. E91-B, No. 5, 01.01.2008, p. 1397-1402.

Research output: Contribution to journalArticle

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