A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect

Jaewon Cha, Wooheon Kang, Junsub Chung, Kunwoo Park, Sungho Kang

Research output: Contribution to journalArticle

1 Citation (Scopus)

Abstract

Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit nand flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50% and thereby improve the cycling time by 19.4% in a 3 ×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80% and thereby improve the endurance test time by 30.8% in a 2 ×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4%.

Original languageEnglish
Article number7101285
Pages (from-to)399-407
Number of pages9
JournalIEEE Transactions on Semiconductor Manufacturing
Volume28
Issue number3
DOIs
Publication statusPublished - 2015 Aug 1

Fingerprint

Flash memory
endurance
flash
Durability
interference
Bit error rate
bit error rate
cells
cycles
Threshold voltage
threshold voltage
constrictions

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Condensed Matter Physics
  • Industrial and Manufacturing Engineering
  • Electrical and Electronic Engineering

Cite this

Cha, Jaewon ; Kang, Wooheon ; Chung, Junsub ; Park, Kunwoo ; Kang, Sungho. / A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect. In: IEEE Transactions on Semiconductor Manufacturing. 2015 ; Vol. 28, No. 3. pp. 399-407.
@article{13ee3cf3504046b9bf7ca842f2eb2a96,
title = "A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect",
abstract = "Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit nand flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50{\%} and thereby improve the cycling time by 19.4{\%} in a 3 ×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80{\%} and thereby improve the endurance test time by 30.8{\%} in a 2 ×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4{\%}.",
author = "Jaewon Cha and Wooheon Kang and Junsub Chung and Kunwoo Park and Sungho Kang",
year = "2015",
month = "8",
day = "1",
doi = "10.1109/TSM.2015.2429211",
language = "English",
volume = "28",
pages = "399--407",
journal = "IEEE Transactions on Semiconductor Manufacturing",
issn = "0894-6507",
publisher = "Institute of Electrical and Electronics Engineers Inc.",
number = "3",

}

A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect. / Cha, Jaewon; Kang, Wooheon; Chung, Junsub; Park, Kunwoo; Kang, Sungho.

In: IEEE Transactions on Semiconductor Manufacturing, Vol. 28, No. 3, 7101285, 01.08.2015, p. 399-407.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A New Accelerated Endurance Test for Terabit NAND Flash Memory Using Interference Effect

AU - Cha, Jaewon

AU - Kang, Wooheon

AU - Chung, Junsub

AU - Park, Kunwoo

AU - Kang, Sungho

PY - 2015/8/1

Y1 - 2015/8/1

N2 - Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit nand flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50% and thereby improve the cycling time by 19.4% in a 3 ×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80% and thereby improve the endurance test time by 30.8% in a 2 ×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4%.

AB - Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit nand flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50% and thereby improve the cycling time by 19.4% in a 3 ×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80% and thereby improve the endurance test time by 30.8% in a 2 ×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4%.

UR - http://www.scopus.com/inward/record.url?scp=84938793547&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=84938793547&partnerID=8YFLogxK

U2 - 10.1109/TSM.2015.2429211

DO - 10.1109/TSM.2015.2429211

M3 - Article

VL - 28

SP - 399

EP - 407

JO - IEEE Transactions on Semiconductor Manufacturing

JF - IEEE Transactions on Semiconductor Manufacturing

SN - 0894-6507

IS - 3

M1 - 7101285

ER -