Limited endurance of E/W cycles is a unique restriction of flash memories and the endurance characteristics usually take a longer time to test. In this paper, we proposed a novel endurance test scheme that takes advantage of the parasitic cell-to-cell interference as well as a shortened program time to accelerate the endurance test for terabit nand flash memory. The novelty of the new scheme is the use of a new test sequence known as even/odd row address sequence (EORAS). The interference effect during the program operation mainly affects the threshold voltage widening in the victim cell and leads to errors linearly during the read operation. We mainly focus on the correlation between the interference and device error rate during the endurance test. Based on the correlation, we use the interference effect as an acceleration factor in EORAS. EORAS is composed of a new program operation for unit test-time reduction. Our experimental results show that the proposed scheme method can induce the raw bit error rate by 50% and thereby improve the cycling time by 19.4% in a 3 ×-nm flash device. The proposed scheme method can also induce the raw bit error rate by 80% and thereby improve the endurance test time by 30.8% in a 2 ×-nm flash device. Consequently, the new endurance scheme reduces the test time by 68.4%.
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Condensed Matter Physics
- Industrial and Manufacturing Engineering
- Electrical and Electronic Engineering