A new built-in self test scheme for phase-locked loops using internal digital signals

Youbean Kim, Kicheol Kim, Incheol Kim, Sungho Kang

Research output: Contribution to journalArticle

4 Citations (Scopus)

Abstract

Testing PLLs (phase-locked loops) is becoming an important issue that affects both time-to-market and production cost of electronic systems. Though a PLL is the most common mixed-signal building block, it is very difficult to test due to internal analog blocks and signals. In this paper, we propose a new PLL BIST (built-in self test) using the distorted frequency detector that uses only internal digital signals. The proposed BIST does not need to load any analog nodes of the PLL. Therefore, it provides an efficient defect-oriented structural test scheme, reduced area overhead, and improved test quality compared with previous approaches.

Original languageEnglish
Pages (from-to)1713-1716
Number of pages4
JournalIEICE Transactions on Electronics
VolumeE91-C
Issue number10
DOIs
Publication statusPublished - 2008 Jan 1

Fingerprint

Built-in self test
Phase locked loops
Detectors
Defects
Testing
Costs

All Science Journal Classification (ASJC) codes

  • Electronic, Optical and Magnetic Materials
  • Electrical and Electronic Engineering

Cite this

Kim, Youbean ; Kim, Kicheol ; Kim, Incheol ; Kang, Sungho. / A new built-in self test scheme for phase-locked loops using internal digital signals. In: IEICE Transactions on Electronics. 2008 ; Vol. E91-C, No. 10. pp. 1713-1716.
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A new built-in self test scheme for phase-locked loops using internal digital signals. / Kim, Youbean; Kim, Kicheol; Kim, Incheol; Kang, Sungho.

In: IEICE Transactions on Electronics, Vol. E91-C, No. 10, 01.01.2008, p. 1713-1716.

Research output: Contribution to journalArticle

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