In this paper, a new normalization design method for a floating-point unit is presented. Shift amount information for normalization is devised to generate leading one position value (LOPV). LOPV is the number with all zero bits except the leading one position. LOPV can be easily generated by two NOR planes, which implies it can be implemented by bit-parallel operations. Therefore, LOPV can be acquired within about a half delay time of conventional leading zero counters (LZC). An additional NOR plane is required to decode the LOPV to shifter control signals. A total of three NOR planes and an actual shifter operation can implement the floating-point normalization. The chip has been fabricated by using a commercial TSMC 0.18 μm 5-metal CMOS technology with 1.8 V supply voltage. The core area is 550 μm x 200 μm and normalization delay has been measured as 1.4 ns.