Error correcting codes (ECCs) are commonly used as a protection against the soft errors. Single error correcting and double error detecting (SECDED) codes are generally used for this purpose. Such circuits are widely used in industry in all types of memory, including caches and embedded memory. In this paper, a new genetic design for ECC is proposed to perform SECDED in the memory check circuit. The design is aimed at finding the implementation of ECC which consumes minimal power. We formulate the ECC design into a permutable optimization problem and employ special genetic operators appropriate for this formulation. Experiments are performed to demonstrate the performance of the proposed method.
All Science Journal Classification (ASJC) codes
- Hardware and Architecture
- Electrical and Electronic Engineering