A scan architecture is the most widely used for obtaining high test coverage in manufacturing tests. However, the recent increase in circuit size has caused the power consumption during scan testing to become higher than that in the functional mode. Thus, the reliability of scan testing has become a concern. In this brief, a new logic topology-based scan chain stitching method is proposed to reduce the test power. The proposed method uses the topology of logic circuits to analyze them without relying on specific test patterns. The proposed method is beneficial for reduction of both computation time and test power during testing with various test patterns. The method performs two processes to consider the shift-in and shift-out powers. The first process, logic topology-based scan partitioning, forms scan chains based on scan estimation value that estimates the shift-out data occurring in flip-flops. The second process, logic topology-based scan stitching, determines the order of the flip-flops by calculating the scan influence value, using which the proposed method can reduce the shift-in power by consolidating the care bit density in the test patterns. The experiments conducted on ISCAS'89 and ITC'99 benchmark circuits demonstrate that on average, the proposed method reduces the shift power by 28.36% compared with a previous logic topology-based scan chain stitching method.
|Number of pages||5|
|Journal||IEEE Transactions on Circuits and Systems II: Express Briefs|
|Publication status||Published - 2020 Dec|
Bibliographical noteFunding Information:
This work was supported by the IT Research and Development Program of MOTIE/KEIT (Design Technology Development of Ultra-Low Voltage Operating Circuit and IP for Smart Sensor SoC) under Grant 10052716.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering