A new maximal diagnosis algorithm for interconnect test

Yongjoon Kim; Hyun Don Kim; Sungho Kang

doi:10.1109/TVLSI.2004.826200

A new maximal diagnosis algorithm for interconnect test

Yongjoon Kim, Hyun Don Kim, Sungho Kang

Department of Electrical and Electronic Engineering

Research output: Contribution to journal › Article › peer-review

14 Citations (Scopus)

Abstract

Interconnect test for highly integrated environments becomes more important in terms of its test time and a complete diagnosis, as the complexity of the circuit increases. Since the board-level interconnect test is based on boundary scan technology, it takes a long test time to apply test vectors serially through a long scan chain. Complete diagnosis is another important issue. Since the board-level test is performed for repair, noticing the faulty position is an essential element of any interconnect test. Generally, the interconnect test algorithms that need a short test time cannot perform the complete diagnosis and the algorithms that perform the complete diagnosis need a lengthy test time. To overcome this problem, a new interconnect test algorithm is developed. The new algorithm can provide the complete diagnosis of all faults with a shorter test time compared to the previous algorithms.

Original language	English
Pages (from-to)	532-537
Number of pages	6
Journal	IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Volume	12
Issue number	5
DOIs	https://doi.org/10.1109/TVLSI.2004.826200
Publication status	Published - 2004 May

Bibliographical note

Funding Information:
Manuscript received August 27, 2002; revised May 22, 2003. This work was supported by the Brain Korea 21 Project in 2003. Y. Kim is with the Computer Systems and Reliable SOC Laboratory Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: yongjoonkim@soc.yonsei.ac.kr; yongjoonkim@yonsei.ac.kr). H. Kim is with System LSI Division, Device Solution Network, Samsung Electronics, Yongin 444-711, Korea (e-mail: hd4318.kim@samsung.com). S. Kang is with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: shkang@yonsei.ac.kr). Digital Object Identifier 10.1109/TVLSI.2004.826200

All Science Journal Classification (ASJC) codes

Software
Hardware and Architecture
Electrical and Electronic Engineering

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note = "Funding Information: Manuscript received August 27, 2002; revised May 22, 2003. This work was supported by the Brain Korea 21 Project in 2003. Y. Kim is with the Computer Systems and Reliable SOC Laboratory Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: yongjoonkim@soc.yonsei.ac.kr; yongjoonkim@yonsei.ac.kr). H. Kim is with System LSI Division, Device Solution Network, Samsung Electronics, Yongin 444-711, Korea (e-mail: hd4318.kim@samsung.com). S. Kang is with the Department of Electrical and Electronic Engineering, Yonsei University, Seoul 120-749, Korea (e-mail: shkang@yonsei.ac.kr). Digital Object Identifier 10.1109/TVLSI.2004.826200",

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