A new network synchronizer using a two-way message exchange is proposed and implemented in a field-programmable gate array (FPGA). This synchronizer aligns its clock signal and time of day to that of the master node. For high-precision frequency control, a new phase adjustment method is employed, which efficiently provides high-frequency resolution and deterministic frequency control gain. In addition, a feedforward filter is used to reduce dithering of the time offset due to quantization errors in time-stamping. Even with a low-cost crystal oscillator, successful synchronization with root-mean-square (RMS) jitters of 0.1856 unit interval is achieved.
|Number of pages||11|
|Journal||IEEE Transactions on Instrumentation and Measurement|
|Publication status||Published - 2010 Jul|
Bibliographical noteFunding Information:
Manuscript received October 29, 2008; revised June 22, 2009; accepted July 4, 2009. Date of publication December 4, 2009; date of current version June 9, 2010. This work was supported by the IT R&D program of the Ministry of Knowledge Economy/Institute for Information Technology Advancement under Project 2009-S043-01 (Scalable Micro Flow Processing Technology Development). The Associate Editor coordinating the review process for this paper was Dr. Domenico Grimaldi.
All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering