A new scan architecture for both low power testing and test volume compression under SOC test environment

Hong Sik Kim, Sungho Kang, Michael S. Hsiao

Research output: Contribution to journalArticle

7 Citations (Scopus)

Abstract

A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

Original languageEnglish
Pages (from-to)365-378
Number of pages14
JournalJournal of Electronic Testing: Theory and Applications (JETTA)
Volume24
Issue number4
DOIs
Publication statusPublished - 2008 Aug 1

Fingerprint

Testing
Freezing
Clocks
Electric power utilization
Networks (circuits)

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering

Cite this

@article{d02a3c528fea4d52a8cbe772f5d5a08e,
title = "A new scan architecture for both low power testing and test volume compression under SOC test environment",
abstract = "A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.",
author = "Kim, {Hong Sik} and Sungho Kang and Hsiao, {Michael S.}",
year = "2008",
month = "8",
day = "1",
doi = "10.1007/s10836-008-5062-6",
language = "English",
volume = "24",
pages = "365--378",
journal = "Journal of Electronic Testing: Theory and Applications (JETTA)",
issn = "0923-8174",
publisher = "Springer Netherlands",
number = "4",

}

A new scan architecture for both low power testing and test volume compression under SOC test environment. / Kim, Hong Sik; Kang, Sungho; Hsiao, Michael S.

In: Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 24, No. 4, 01.08.2008, p. 365-378.

Research output: Contribution to journalArticle

TY - JOUR

T1 - A new scan architecture for both low power testing and test volume compression under SOC test environment

AU - Kim, Hong Sik

AU - Kang, Sungho

AU - Hsiao, Michael S.

PY - 2008/8/1

Y1 - 2008/8/1

N2 - A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

AB - A new scan architecture for both low power testing and test volume compression is proposed. For low power test requirements, only a subset of scan cells is loaded with test stimulus and captured with test responses by freezing the remaining scan cells according to the distribution of unspecified bits in the test cubes. In order to optimize the proposed process, a novel graph-based heuristic is proposed to partition the scan chains into several segments. For test volume reduction, a new LFSR reseeding based test compression scheme is proposed by reducing the maximum number of specified bits in the test cube set, s max, virtually. The performance of a conventional LFSR reseeding scheme highly depends on s max. In this paper, by using different clock phases between an LFSR and scan chains, and grouping the scan cells by a graph-based grouping heuristic, s max could be virtually reduced. In addition, the reduced scan rippling in the proposed test compression scheme can contribute to reduce the test power consumption, while the reuse of some test results as the subsequent test stimulus in the low power testing scheme can reduce the test volume size. Experimental results on the largest ISCAS89 benchmark circuits show that the proposed technique can significantly reduce both the average switching activity and the peak switching activity, and can aggressively reduce the volume of the test data, with little area overhead, compared to the previous methods.

UR - http://www.scopus.com/inward/record.url?scp=44649117590&partnerID=8YFLogxK

UR - http://www.scopus.com/inward/citedby.url?scp=44649117590&partnerID=8YFLogxK

U2 - 10.1007/s10836-008-5062-6

DO - 10.1007/s10836-008-5062-6

M3 - Article

VL - 24

SP - 365

EP - 378

JO - Journal of Electronic Testing: Theory and Applications (JETTA)

JF - Journal of Electronic Testing: Theory and Applications (JETTA)

SN - 0923-8174

IS - 4

ER -