Scan-based testing, though widely used in modern digital designs, causes more power consumption than in functional mode. This excessive power consumption can cause severe hazards such as circuit reliability and yield loss. To solve this problem, a new scan chain reordering method based on care bit density is proposed in this paper. This proposed method helps merging care bits toward the front end of scan chains. Thus, it can reduce scan cell switching activities during scan shift operation. Experimental results on ISCAS'89 benchmark circuits show that the proposed scan chain reordering method reduces test power consumption compared to the previous work.
|Title of host publication||Proceedings - 2019 International SoC Design Conference, ISOCC 2019|
|Publisher||Institute of Electrical and Electronics Engineers Inc.|
|Number of pages||2|
|Publication status||Published - 2019 Oct 1|
|Event||16th International System-on-Chip Design Conference, ISOCC 2019 - Jeju, Korea, Republic of|
Duration: 2019 Oct 6 → 2019 Oct 9
|Name||Proceedings - 2019 International SoC Design Conference, ISOCC 2019|
|Conference||16th International System-on-Chip Design Conference, ISOCC 2019|
|Country/Territory||Korea, Republic of|
|Period||19/10/6 → 19/10/9|
Bibliographical noteFunding Information:
ACKNOWLEDGMENT This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].
This work was supported by the IT R&D program of MOTIE/KEIT. [10052716, Design technology development of ultra-low voltage operating circuit and IP for smart sensor SoC].
© 2019 IEEE.
All Science Journal Classification (ASJC) codes
- Signal Processing
- Electrical and Electronic Engineering
- Artificial Intelligence
- Hardware and Architecture