Abstract
This paper presents a new slot synchronization scheme robust to timing errors for W-CDMA when the slot synchronization scheme is performed using a resolution of two samples per chip. The proposed scheme uses the sum of consecutive complex matched filter outputs to calculate the decision variables of all possible slot starting positions. Simulation results show that the maximum gain of the proposed scheme is about 2 dB compared to the conventional one.
| Original language | English |
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| Pages (from-to) | 2038-2041 |
| Number of pages | 4 |
| Journal | IEEE Vehicular Technology Conference |
| Volume | 57 |
| Issue number | 3 |
| Publication status | Published - 2003 |
| Event | 57th IEEE Semiannual Vehicular Technology Conference (VTC2003) - Jeju, Korea, Republic of Duration: 2003 Apr 22 → 2003 Apr 25 |
All Science Journal Classification (ASJC) codes
- Computer Science Applications
- Electrical and Electronic Engineering
- Applied Mathematics