A new slot synchronization scheme robust to timing errors for W-CDMA

Sang Yun Hwang, Jae Seok Kim

Research output: Contribution to journalConference article

Abstract

This paper presents a new slot synchronization scheme robust to timing errors for W-CDMA when the slot synchronization scheme is performed using a resolution of two samples per chip. The proposed scheme uses the sum of consecutive complex matched filter outputs to calculate the decision variables of all possible slot starting positions. Simulation results show that the maximum gain of the proposed scheme is about 2 dB compared to the conventional one.

Original languageEnglish
Pages (from-to)2038-2041
Number of pages4
JournalIEEE Vehicular Technology Conference
Volume57
Issue number3
Publication statusPublished - 2003 Sep 1
Event57th IEEE Semiannual Vehicular Technology Conference (VTC2003) - Jeju, Korea, Republic of
Duration: 2003 Apr 222003 Apr 25

Fingerprint

WCDMA
Code division multiple access
Timing
Synchronization
Matched filters
Matched Filter
Consecutive
Chip
Calculate
Output
Simulation

All Science Journal Classification (ASJC) codes

  • Computer Science Applications
  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

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abstract = "This paper presents a new slot synchronization scheme robust to timing errors for W-CDMA when the slot synchronization scheme is performed using a resolution of two samples per chip. The proposed scheme uses the sum of consecutive complex matched filter outputs to calculate the decision variables of all possible slot starting positions. Simulation results show that the maximum gain of the proposed scheme is about 2 dB compared to the conventional one.",
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A new slot synchronization scheme robust to timing errors for W-CDMA. / Hwang, Sang Yun; Kim, Jae Seok.

In: IEEE Vehicular Technology Conference, Vol. 57, No. 3, 01.09.2003, p. 2038-2041.

Research output: Contribution to journalConference article

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