Abstract
Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposedmethodology consists of a defect-based wafer burn-in (DBWBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.
| Original language | English |
|---|---|
| Title of host publication | Proceedings - International Test Conference 2008, ITC 2008 |
| DOIs | |
| Publication status | Published - 2008 Dec 1 |
| Event | International Test Conference 2008, ITC 2008 - Santa Clara, CA, United States Duration: 2008 Oct 28 → 2008 Oct 30 |
Publication series
| Name | Proceedings - International Test Conference |
|---|---|
| ISSN (Print) | 1089-3539 |
Other
| Other | International Test Conference 2008, ITC 2008 |
|---|---|
| Country | United States |
| City | Santa Clara, CA |
| Period | 08/10/28 → 08/10/30 |
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All Science Journal Classification (ASJC) codes
- Electrical and Electronic Engineering
- Applied Mathematics
Cite this
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A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method. / Nam, Junghyun; Chun, Sunghoon; Koo, Gibum; Kim, Yanggi; Moon, Byungsoo; Lim, Jonghyoung; Joo, Jaehoon; Kang, Sangseok; Kim, Hoonjung; Shin, Kyeongseon; Kang, Kisang; Kang, Sungho.
Proceedings - International Test Conference 2008, ITC 2008. 2008. 4700632 (Proceedings - International Test Conference).Research output: Chapter in Book/Report/Conference proceeding › Conference contribution
TY - GEN
T1 - A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method
AU - Nam, Junghyun
AU - Chun, Sunghoon
AU - Koo, Gibum
AU - Kim, Yanggi
AU - Moon, Byungsoo
AU - Lim, Jonghyoung
AU - Joo, Jaehoon
AU - Kang, Sangseok
AU - Kim, Hoonjung
AU - Shin, Kyeongseon
AU - Kang, Kisang
AU - Kang, Sungho
PY - 2008/12/1
Y1 - 2008/12/1
N2 - Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposedmethodology consists of a defect-based wafer burn-in (DBWBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.
AB - Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposedmethodology consists of a defect-based wafer burn-in (DBWBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.
UR - http://www.scopus.com/inward/record.url?scp=67249126197&partnerID=8YFLogxK
UR - http://www.scopus.com/inward/citedby.url?scp=67249126197&partnerID=8YFLogxK
U2 - 10.1109/TEST.2008.4700632
DO - 10.1109/TEST.2008.4700632
M3 - Conference contribution
AN - SCOPUS:67249126197
SN - 9781424424030
T3 - Proceedings - International Test Conference
BT - Proceedings - International Test Conference 2008, ITC 2008
ER -