A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method

Junghyun Nam, Sunghoon Chun, Gibum Koo, Yanggi Kim, Byungsoo Moon, Jonghyoung Lim, Jaehoon Joo, Sangseok Kang, Hoonjung Kim, Kyeongseon Shin, Kisang Kang, Sungho Kang

Research output: Chapter in Book/Report/Conference proceedingConference contribution

Abstract

Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposedmethodology consists of a defect-based wafer burn-in (DBWBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6%. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.

Original languageEnglish
Title of host publicationProceedings - International Test Conference 2008, ITC 2008
DOIs
Publication statusPublished - 2008 Dec 1
EventInternational Test Conference 2008, ITC 2008 - Santa Clara, CA, United States
Duration: 2008 Oct 282008 Oct 30

Publication series

NameProceedings - International Test Conference
ISSN (Print)1089-3539

Other

OtherInternational Test Conference 2008, ITC 2008
CountryUnited States
CitySanta Clara, CA
Period08/10/2808/10/30

Fingerprint

Response Surface Method
Dynamic random access storage
Burn-in
Wafer
Screening
Defects
Methodology
Manufacturing
Costs
Die
Data storage equipment
Fabrication
Testing
Optimization Methods
Experimental Data
Requirements
Experimental Results

All Science Journal Classification (ASJC) codes

  • Electrical and Electronic Engineering
  • Applied Mathematics

Cite this

Nam, J., Chun, S., Koo, G., Kim, Y., Moon, B., Lim, J., ... Kang, S. (2008). A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method. In Proceedings - International Test Conference 2008, ITC 2008 [4700632] (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2008.4700632
Nam, Junghyun ; Chun, Sunghoon ; Koo, Gibum ; Kim, Yanggi ; Moon, Byungsoo ; Lim, Jonghyoung ; Joo, Jaehoon ; Kang, Sangseok ; Kim, Hoonjung ; Shin, Kyeongseon ; Kang, Kisang ; Kang, Sungho. / A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method. Proceedings - International Test Conference 2008, ITC 2008. 2008. (Proceedings - International Test Conference).
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abstract = "Screening latent defects in a wafer test process is very important task in both reducing memory manufacturing cost and enhancing the reliability of emerging package products such as SIP, MCP, and WSP. In terms of the package assembly cost, these package products are required to adopt the KGD (known good die) quality level. However, the KGD requires a long burn-in time, added testing time, and high cost equipments. To alleviate these problems, this paper presents a statistical wafer burn-in methodology for the latent defect screen in the wafer test process. The newly proposedmethodology consists of a defect-based wafer burn-in (DBWBI) stress method based on DRAM operation characteristics and a statistical stress optimization method using RSM (response surface method) on the DRAM manufacturing test process. Experimental data shows that package test yields in the immature fabrication process improved by up to 6{\%}. In addition, experimental results show that the proposed methodology can guarantee reliability requirements with a shortened package burn-in time. In conclusion, this methodology realizes a simplified manufacturing test process supporting time to market with high reliability.",
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Nam, J, Chun, S, Koo, G, Kim, Y, Moon, B, Lim, J, Joo, J, Kang, S, Kim, H, Shin, K, Kang, K & Kang, S 2008, A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method. in Proceedings - International Test Conference 2008, ITC 2008., 4700632, Proceedings - International Test Conference, International Test Conference 2008, ITC 2008, Santa Clara, CA, United States, 08/10/28. https://doi.org/10.1109/TEST.2008.4700632

A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method. / Nam, Junghyun; Chun, Sunghoon; Koo, Gibum; Kim, Yanggi; Moon, Byungsoo; Lim, Jonghyoung; Joo, Jaehoon; Kang, Sangseok; Kim, Hoonjung; Shin, Kyeongseon; Kang, Kisang; Kang, Sungho.

Proceedings - International Test Conference 2008, ITC 2008. 2008. 4700632 (Proceedings - International Test Conference).

Research output: Chapter in Book/Report/Conference proceedingConference contribution

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Nam J, Chun S, Koo G, Kim Y, Moon B, Lim J et al. A new wafer level latent defect screening methodology for highly reliable DRAM using a response surface method. In Proceedings - International Test Conference 2008, ITC 2008. 2008. 4700632. (Proceedings - International Test Conference). https://doi.org/10.1109/TEST.2008.4700632