Abstract
Built-in redundancy analysis (BIRA) is widely used to enhance the yield of embedded memories. In this letter, a new BIRA method for both high repair efficiency and small hardware overhead is presented. The proposed method performs redundancy analysis operations using the spare mapping registers with a covered fault list. Experimental results demonstrate the superiority of the proposed method compared to previous works.
| Original language | English |
|---|---|
| Pages (from-to) | 339-341 |
| Number of pages | 3 |
| Journal | ETRI Journal |
| Volume | 31 |
| Issue number | 3 |
| DOIs | |
| Publication status | Published - 2009 Jun |
All Science Journal Classification (ASJC) codes
- Electronic, Optical and Magnetic Materials
- Computer Science(all)
- Electrical and Electronic Engineering