A novel charge pump PLL with reduced jitter characteristics

Myoung Su Lee, Tae Sik Cheung, Woo Young Choi

Research output: Chapter in Book/Report/Conference proceedingConference contribution

7 Citations (Scopus)

Abstract

A new charge pump structure is proposed that can improve jitter characteristics of a Phase-Locked Loop (PLL) by blocking the control voltage leakages. The new structure also has low power consumption because it uses a self-biased method that switches the current flow only on demand. A PLL with the proposed charge pump is designed with 0.6 μm CMOS process technology and evaluated by post-layout simulation.

Original languageEnglish
Title of host publicationICVC 1999 - 6th International Conference on VLSI and CAD
PublisherInstitute of Electrical and Electronics Engineers Inc.
Pages596-598
Number of pages3
ISBN (Print)0780357272, 9780780357273
DOIs
Publication statusPublished - 1999 Jan 1
Event6th International Conference on VLSI and CAD, ICVC 1999 - Seoul, Korea, Republic of
Duration: 1999 Oct 261999 Oct 27

Publication series

NameICVC 1999 - 6th International Conference on VLSI and CAD

Other

Other6th International Conference on VLSI and CAD, ICVC 1999
CountryKorea, Republic of
CitySeoul
Period99/10/2699/10/27

All Science Journal Classification (ASJC) codes

  • Computer Graphics and Computer-Aided Design
  • Hardware and Architecture
  • Electrical and Electronic Engineering
  • Electronic, Optical and Magnetic Materials

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  • Cite this

    Lee, M. S., Cheung, T. S., & Choi, W. Y. (1999). A novel charge pump PLL with reduced jitter characteristics. In ICVC 1999 - 6th International Conference on VLSI and CAD (pp. 596-598). [821010] (ICVC 1999 - 6th International Conference on VLSI and CAD). Institute of Electrical and Electronics Engineers Inc.. https://doi.org/10.1109/ICVC.1999.821010